Output Buffer Latch Control for Fast Low-to-High Level Shifting
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Solution Overview
Problem
Output buffer circuits face challenges in increasing switching rate while reducing power consumption due to large gate-to-drain parasitic capacitance in pull-up transistors when transferring low-voltage control signals to high-voltage circuits.
Innovation Solution
The output buffer circuit employs a configuration with a pull-up transistor and a pull-down transistor connected between a high power supply voltage and a reference voltage, utilizing a latch circuit to control the pull-up transistor and a level shifter to manage signal changes, which improves switching rate and reduces current consumption by minimizing gate-to-source voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional output buffer circuit with a pull-up transistor is used to transfer low-voltage control signals to high-voltage circuits, then the circuit can perform voltage level conversion, but the large gate-to-drain parasitic capacitance in the pull-up transistor prevents simultaneous improvement of switching rate and reduction of power consumption
Solution Approach 1:
The patent segments the control signal generation into two independent parts: a first control signal for the pull-down transistor and a second control signal for the pull-up transistor. This segmentation allows each transistor to be controlled optimally without the other interfering, enabling the pull-up transistor to be turned off during low-to-high transitions to minimize parasitic capacitance charging, thus improving switching rate while reducing power consumption.
Solution Approach 2:
The patent dynamically adjusts the control signals based on the required transition direction. The first driving circuit generates a control signal that dynamically turns off the pull-down transistor during low-to-high output transitions, while the second driving circuit independently controls the pull-up transistor. This dynamic control minimizes the charging of parasitic capacitance and reduces unnecessary current flow, simultaneously improving switching rate and reducing power consumption.
2Device complexity
If the pull-up transistor is controlled directly by a low-voltage control signal, then the control is simple, but the gate-to-drain parasitic capacitance causes high power consumption and slow switching
Solution Approach 1:
The patent introduces a second driving circuit as an intermediary between the low-voltage control signal and the pull-up transistor. This intermediary circuit generates an optimized second control signal that independently controls the pull-up transistor, allowing for minimal gate-to-drain parasitic capacitance charging. This adds some complexity but enables significantly faster switching rates by preventing unnecessary capacitance charging.
3Reliability
If the pull-up transistor is controlled with a level-shifted high-voltage signal, then voltage level conversion is achieved, but the gate-to-drain parasitic capacitance still causes high power consumption
Solution Approach 1:
The patent employs feedback mechanisms in both driving circuits to optimize power consumption. The first driving circuit feedback-controls the pull-down transistor to turn it off during low-to-high transitions, preventing unnecessary current flow through the pull-up transistor's parasitic capacitance. The second driving circuit independently feedback-controls the pull-up transistor based on the desired output transition, minimizing the charging of parasitic capacitance and reducing power consumption while maintaining reliable voltage level conversion.
Data Source
AI summary
An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes.