Output Buffer ODT Circuit for Low-Leak Non-Selected Operation
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Solution Overview
Problem
Semiconductor devices with ODT function experience increased leak current when performing non-target ODT operations in a non-selected state due to the use of transistors with low threshold voltage in the output buffer circuit, affecting data path speed and efficiency.
Innovation Solution
The semiconductor device incorporates a configuration with N-channel MOS transistors having thick gate insulating films and tristate buffer circuits to manage impedance and reduce sub-threshold leak currents, utilizing specific control signals and gate configurations to optimize transistor operation during ODT operations, ensuring accurate impedance calibration and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors with low threshold voltage are used in the output buffer circuit to increase data path speed, then the speed of data path to the output buffer is improved, but the leak current increases when the semiconductor device is in a non-selected state
Solution Approach 1:
The patent divides the transistor gate insulating film into two segments: a first gate insulating film with a first thickness and a second gate insulating film with a second thickness greater than the first. This segmentation allows different regions of the gate to have different thicknesses, enabling the transistor to achieve both high-speed operation (through the thinner first gate insulating film region) and low leak current (through the thicker second gate insulating film region), thereby resolving the contradiction between speed and energy loss.
2Measurement precision
If non-target ODT operation is performed to make the output buffer function as a terminating resistor, then the impedance is calibrated accurately, but the leak current increases when the semiconductor device is in a non-selected state
Solution Approach 1:
The patent applies local quality by creating a gate insulating film with non-uniform thickness, where the first gate insulating film has a first thickness optimized for one function and the second gate insulating film has a second thickness optimized for another function. This local differentiation allows the transistor to perform non-target ODT operation with accurate impedance calibration while maintaining low leak current in the non-selected state, resolving the contradiction between measurement precision and energy loss.
3Power
If transistors with low threshold voltage are used to increase data path speed, then the driving capability is improved, but the sub-threshold leak currents increase
Solution Approach 1:
The segmented gate insulating film structure allows the transistor to have regions with different threshold characteristics. The thinner first gate insulating film provides strong electric field for high driving capability, while the thicker second gate insulating film provides better barrier against sub-threshold leak currents. This segmentation resolves the contradiction between power (driving capability) and energy loss (sub-threshold leak current).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces leak currents and improves driving capability during non-target ODT operations, enhancing the semiconductor device's efficiency and reliability by minimizing process variation impacts and preventing charge injection during high-speed switching.
Implementation Method 1
N-channel MOS transistors with thick gate insulating films are used to reduce sub-threshold leak currents
Implementation Method 2
minimizing process variation impacts and preventing charge injection during high-speed switching
Data Source
AI summary
Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.