Semiconductor Output Buffer Impedance Calibration
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Solution Overview
Problem
Existing impedance adjustment methods in semiconductor devices face challenges due to variations in interconnect resistance, which affect the accuracy of impedance calibration in output circuits, particularly in DRAMs, where the length of interconnects between transistors and output terminals differs, leading to inconsistent impedance adjustments.
Innovation Solution
The implementation of a configuration where multiple unitary buffers with adjustable impedances are coupled in parallel, with front-stage circuits determining which transistors to activate based on selection signals, allowing for collective impedance adjustment by a single calibration circuit, thereby simplifying the calibration process and reducing impedance variance caused by interconnect resistance differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple transistors are coupled in parallel for impedance adjustment, then the range of impedance adjustment is improved, but the interconnect resistance variance worsens due to different interconnect lengths
Solution Approach 1:
The patent applies local quality by making the interconnect structure uniform for all transistors. Specifically, all transistors are connected to the output terminal through interconnects of the same length and configuration, ensuring that each transistor experiences identical interconnect resistance. This local uniformity eliminates the variance in interconnect resistance that would otherwise occur with different interconnect lengths, thereby maintaining impedance calibration accuracy while allowing wide impedance adjustment range through parallel transistor configuration.
2Device complexity
If a single calibration circuit adjusts multiple unitary buffers, then the device complexity is reduced, but the measurement precision of impedance calibration may worsen
Solution Approach 1:
The patent merges multiple calibration functions into a single calibration circuit. The calibration circuit is configured to simultaneously adjust the impedances of multiple unitary buffers by controlling the activation of transistors in each buffer. This consolidation reduces device complexity by eliminating the need for separate calibration circuits for each buffer, while the uniform interconnect design ensures that the single calibration circuit maintains measurement precision across all buffers.
3Adaptability or versatility
If transistors are selected for activation based on binary-weighted configuration, then the impedance adjustment stages are increased, but the interconnect resistance difference becomes more significant
Solution Approach 1:
The patent applies local quality by ensuring that the interconnect structure is locally uniform for all transistors regardless of their position in the binary-weighted configuration. Each transistor, whether activated or not, connects to the output terminal through an interconnect of identical length and characteristics. This local uniformity ensures that interconnect resistance remains consistent across all transistor selections, eliminating the resistance differences that would otherwise arise from varying interconnect lengths in binary-weighted impedance adjustment.
Data Source
AI summary
An output circuit includes first, second and third transistors. The first transistor includes first and second diffusion layers. The third transistor includes third and fourth diffusion layers. The first transistor shares the second diffusion layer with the second transistor and the third transistor shares the third diffusion layer with the second transistor. The second transistor is rendered conductive responsive to an activation of a first signal and non-conductive responsive to an inactivation of the first signal. The first and third transistors are rendered conductive responsive to an activation of a second signal that is different from the first signal and rendered non-conductive responsive to an in activation of the second signal.