Output Buffer Voltage Switching for Retention Mode Signals
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Solution Overview
Problem
Computer systems face challenges in maintaining usable output signals from circuit blocks operating in retention mode, as the reduced voltage level makes signals unconsumable by other blocks, requiring careful scheduling to avoid placing circuit blocks in retention mode during signal supply.
Innovation Solution
An output buffer circuit that selectively couples either a power supply node or a retention supply node to a local supply node using switch control signals, allowing the generation of output signals at a voltage level consumable by other blocks even when the circuit block is in retention mode, using a switch circuit and latch circuit to manage voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the voltage level of the power supply is reduced to enter retention mode, then power consumption is reduced, but the output signal voltage level becomes too low to be consumed by other circuit blocks
Solution Approach 1:
The power supply is segmented into multiple independent sources: a first power supply node providing full voltage for active mode, and a second power supply node providing reduced voltage for retention mode. The circuit block can selectively receive power from either node, allowing it to operate in retention mode with reduced power consumption while maintaining the ability to generate full-voltage output signals when needed.
Solution Approach 2:
Before transitioning to retention mode, the circuit block generates and stores output signals at the higher voltage level. This preliminary action ensures that when the circuit block enters retention mode with reduced voltage, the previously stored high-voltage signals are still available for consumption by other circuit blocks, resolving the contradiction between power savings and signal usability.
2Use of energy by moving object
If the voltage level of the power supply is reduced to enter retention mode, then power consumption is reduced, but the circuit block cannot perform operations at desired speed
Solution Approach 1:
The power supply system is divided into distinct voltage levels delivered through separate power supply nodes. The first node provides sufficient voltage for high-speed operations, while the second node provides reduced voltage for low-power retention. This segmentation allows the circuit block to switch between operational states without compromise.
Solution Approach 2:
The circuit block dynamically transitions between two operational states: active mode with full voltage for high-speed operations, and retention mode with reduced voltage for power saving. The ability to switch between these states allows the system to optimize between speed and power consumption based on real-time requirements.
3Reliability
If careful scheduling is implemented to prevent placing circuit blocks in retention mode during signal supply, then output signal usability is maintained, but system complexity and control overhead increase
Solution Approach 1:
By segmenting the power supply into separate nodes, the system eliminates the need for complex scheduling logic. The circuit block can independently manage its power state based on simple control signals, rather than requiring coordinated scheduling with other system components. This reduces control overhead while maintaining signal usability.
Solution Approach 2:
The circuit block is designed to autonomously manage its transition between active and retention modes based on simple control inputs. Rather than requiring external scheduling coordination, the circuit block self-manages its power state and signal generation, simplifying the overall system control architecture.
Data Source
AI summary
A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.