Output Buffer Circuit Timing to Prevent Through Current
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Solution Overview
Problem
Existing output buffer circuits in display drive devices experience increased power consumption and noise due to simultaneous switching of transistors, leading to large circuit areas and reduced response speed, exacerbated by the need for numerous transistors to prevent through currents.
Innovation Solution
An output buffer circuit utilizing a configuration of eight transistors, including inverters and P-channel and N-channel transistors, adjusts switching timings to prevent simultaneous transistor turn-on, reducing circuit area and parasitic capacitance while enabling high-speed response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the timing adjustment part includes OR circuit and AND circuit with six transistors each to prevent simultaneous turn-on, then through current is suppressed, but the total transistor count reaches twelve and circuit area becomes large
Solution Approach 1:
The patent merges the timing adjustment function with the output buffer structure by sharing transistors between the two functions. The fourth transistor serves both as part of the output buffer and as the timing adjustment element, eliminating the need for separate OR and AND circuits. This integration reduces the total transistor count from twelve to eight while maintaining the ability to prevent simultaneous turn-on of the output transistors.
Solution Approach 2:
The fourth transistor performs multiple functions: it acts as an output transistor in the push-pull configuration and simultaneously serves as the timing adjustment element that prevents simultaneous conduction. This multi-functionality reduces the overall circuit complexity and transistor count while achieving both output buffering and timing control.
2Speed
If transistor size is increased to enable quick turn-on and turn-off, then switching speed improves, but circuit area and parasitic capacitance increase
Solution Approach 1:
The patent optimizes the switching speed by carefully selecting and adjusting transistor parameters rather than simply increasing size. The configuration uses six transistors with specific sizing relationships that enable fast switching while controlling parasitic capacitance. The timing adjustment mechanism allows precise control of switching transitions without requiring excessively large transistor dimensions.
3Speed
If six transistors are used in OR and AND circuits for timing adjustment, then transistor turn-on and turn-off speed improves, but the number of transistors increases to twelve
Solution Approach 1:
The patent combines the timing adjustment function with the output buffer structure by sharing transistors between the two functions. The fourth transistor serves both as part of the output buffer and as the timing adjustment element, eliminating the need for separate OR and AND circuits. This integration reduces the total transistor count from twelve to eight while maintaining the ability to prevent simultaneous turn-on of the output transistors.
Solution Approach 2:
The fourth transistor performs multiple functions: it acts as an output transistor in the push-pull configuration and simultaneously serves as the timing adjustment element that prevents simultaneous conduction. This multi-functionality reduces the overall circuit complexity and transistor count while achieving both output buffering and timing control.
Data Source
AI summary
An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.