Memory Chip Output Buffer Calibration Using a ZQ Reference Chip
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Solution Overview
Problem
Current memory systems with NAND flash memory require lengthy calibration operations for output impedance, which can be time-consuming and inefficient, especially when calibrating multiple semiconductor storage devices.
Innovation Solution
A semiconductor device architecture that includes a reference resistor and a controller to perform ZQ calibration and subsequent chip calibration operations, utilizing replica buffer circuits and output buffer controllers to adjust output impedance, allowing for parallel calibration of multiple chips and reducing overall calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ZQ calibration operation is performed for each semiconductor storage device sequentially, then output impedance precision is maintained, but calibration time becomes excessively long
Solution Approach 1:
The calibration process is segmented into two distinct phases: ZQ calibration performed once on a reference chip to establish precise impedance characteristics, and subsequent chip calibration performed in parallel on multiple devices using the reference chip as a template. This segmentation allows precision calibration to be performed only once while enabling rapid parallel calibration of remaining devices.
Solution Approach 2:
The reference chip undergoes complete ZQ calibration in advance before other chips are calibrated. The calibrated reference chip then serves as a template for subsequent parallel calibration operations, eliminating the need to repeat the time-consuming ZQ calibration process for each device while maintaining equivalent precision.
2Productivity
If parallel calibration of multiple chips is implemented, then calibration time is reduced, but calibration precision may deteriorate
Solution Approach 1:
The calibrated reference chip serves as a master template that is copied to multiple subsequent chips through parallel calibration operations. Each subsequent chip receives calibration data from the reference chip, ensuring that all chips achieve equivalent precision without requiring individual ZQ calibration, thus maintaining measurement accuracy while enabling parallel processing.
3Productivity
If additional calibration circuits are added to achieve parallel calibration, then calibration efficiency improves, but device complexity increases
Solution Approach 1:
The reference chip performs multiple functions: it undergoes ZQ calibration to establish precise impedance characteristics, then serves as a calibration template for subsequent chips, and finally can be disabled to allow other chips to become new reference chips. This multi-functionality enables parallel calibration without requiring dedicated calibration circuits, maintaining device simplicity while achieving high throughput.
Solution Approach 2:
The reference chip calibrates itself through ZQ calibration, then uses its own calibrated characteristics to calibrate subsequent chips autonomously. This self-service mechanism eliminates the need for external calibration equipment or additional control circuits, achieving parallel calibration capability without increasing device complexity.
Data Source
AI summary
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.