Output Circuit Clocking for Low-Power High-Speed Serialization
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Solution Overview
Problem
High-speed operation of output circuits in data transmission interfaces leads to significant power consumption and reduced operational margins due to the use of high-frequency clocks, particularly in phase adjustment units, which results in large circuit area and power consumption issues.
Innovation Solution
The implementation of a two-clocks flip-flop circuit (2CLK-FF) operating at the reference clock frequency, along with latency expansion and phase adjustment circuits, reduces power consumption and increases operational margins by using a reference clock as the control clock and arranging DLLs for individual bits on common clock paths, eliminating the need for high-speed clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the last stage converts 2-bits parallel data to 1-bit serial data at double frequency of transmission clock, then the data transmission speed is improved, but power consumption increases and operational margin decreases
Solution Approach 1:
The patent applies dynamic frequency scaling by operating different stages at different clock frequencies. The first stage operates at double frequency (2.133 GHz) to achieve high-speed data conversion, while the second stage operates at half frequency (1.066 GHz) to reduce power consumption. This dynamic frequency adaptation allows the circuit to optimize between speed and power consumption based on stage requirements.
2Stability of the object's composition
If multiple DLLs are provided for output circuits of M-bits, then phase adjustment is achieved, but rising edges/falling edges of outputs do not coincide and circuit area increases
Solution Approach 1:
The patent merges multiple DLL circuits into a shared common DLL structure. Instead of providing separate DLLs for each output block, a single common DLL generates reference clocks that are distributed to multiple output blocks. This merging approach maintains phase adjustment capability while significantly reducing circuit area and ensuring synchronized rising/falling edges across all outputs.
3Productivity
If the last stage operates at double frequency of transmission clock, then data conversion is achieved, but operational margin becomes small
Solution Approach 1:
The patent segments the data conversion process into two distinct stages with different frequency requirements. The first stage performs the high-speed parallel-to-serial conversion at double frequency, while the second stage performs latency adjustment at half frequency. This segmentation allows each stage to operate at optimal frequency, maintaining high productivity in the first stage while ensuring reliability with adequate operational margin in the second stage.
Data Source
AI summary
An output circuit includes: an output portion which includes a plurality of output blocks each of which converts 2-bits parallel data to 1-bit serial data and outputs the converted serial data; a control signal generation circuit; a first clock generation portion; and a plurality of second clock generation portions which individually generate second clocks, wherein each of the output blocks includes: a latency expansion circuit which sequentially latches the 2-bits parallel data according to the reference clock and an inverted reference clock, selects two from the latched data signals based on the latency adjustment signal; and two-clocks flip-flop circuit which latches one of two outputs from the latency expansion circuit in synchronization with the second clock corresponding to the output block and latches the other of the two outputs from the latency expansion circuit in synchronization with the inverted second clock.