Output Control Circuit Timing to Shorten Level-Shift Dead Time

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Solution Overview

Problem

Conventional output control circuits require a level shift circuit, which limits the minimum dead time due to added delay times, necessitating a solution that can shorten the dead time while maintaining the level shift circuit.

Innovation Solution

Incorporating a delay circuit with a longer delay time than the level shift circuit and utilizing a faster level shift circuit in the path of the high-side switch control signal, along with optional precharge and dual-output delay configurations, to extend the on-time of the switch and minimize dead time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a level shift circuit is added in the stage preceding the high-side switch or in the path of its control signal, then the control signal level is properly shifted, but the dead time increases due to the added delay time of the level shift circuit

Engineering Contradiction:
Improvecontrol signal level shiftingVSAvoiddead time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The control circuit generates the high-side switch control signal in advance before the low-side switch turns off. By predicting the timing based on the control signal for the low-side switch, the high-side switch is turned on beforehand, eliminating the dead time while ensuring proper signal level shifting through the level shift circuit.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention dynamically adjusts the timing of the high-side switch control signal based on the operational state of the low-side switch. The control circuit continuously monitors the low-side switch control signal and generates the high-side switch signal at an optimized timing that adapts to changing operating conditions, thereby minimizing dead time while maintaining reliable level shifting.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the dead time is shortened, then the circuit efficiency is improved, but it becomes difficult to maintain proper signal level shifting with existing level shift circuits

Engineering Contradiction:
Improvecircuit efficiencyVSAvoidsignal level shifting
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The control circuit generates the high-side switch control signal in advance before the low-side switch turns off. By predicting the timing based on the control signal for the low-side switch, the high-side switch is turned on beforehand, eliminating the dead time while ensuring proper signal level shifting through the level shift circuit.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The control circuit acts as an intermediary that receives the control signal for the low-side switch and generates an optimized control signal for the high-side switch. This intermediary function allows the system to maintain proper signal level shifting while achieving shorter dead time by inserting a smart control layer between the input signal and the switch devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250300659A1Output control circuit and voltage output circuit
Publication Date: 2025.09.25 ABLIC INC
  • US20250300659A1 patent drawing
  • US20250300659A1 patent drawing
  • US20250300659A1 patent drawing

AI summary

An output control circuit and a voltage output circuit are provided. The output control circuit includes: a first output terminal and a second output terminal connected to a first switch and a second switch respectively, an input terminal, a first level shift circuit, a delay circuit that outputs a signal received after a delay time set longer than a delay time of the first level shift circuit, a second level shift circuit that level-shifts a signal received by an input port connected to an output port of the delay circuit and outputs a level-shifted signal, and a control circuit that outputs a signal with a signal level determined to be either a first level or a second level based on signal levels of signals received from two input ports.