Output Circuit Calibration for Impedance Matching and Low Power
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Solution Overview
Problem
Semiconductor devices face signal distortion due to noise and impedance mismatching during data transmission, which existing on-die termination circuits struggle to address effectively, especially with PVT variations affecting impedance matching.
Innovation Solution
A semiconductor device incorporating a calibration circuit that generates impedance calibration codes and correction codes to minimize power consumption by inverting or maintaining logic levels, which are used by the output circuit to generate signals that optimize impedance matching and reduce signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die termination circuit is used for impedance matching, then signal integrity is improved, but power consumption increases due to continuous calibration operations
Solution Approach 1:
The patent inverts the conventional calibration approach by generating correction calibration codes through logic level inversion of pull-up and pull-down calibration codes. This inversion mechanism enables precise impedance matching with reduced calibration operations, thereby lowering power consumption while maintaining signal integrity.
Solution Approach 2:
The patent changes the parameter representation by using correction calibration codes generated through logic level inversion instead of direct calibration codes. This parameter transformation allows the output circuit to achieve optimal impedance matching with reduced calibration overhead and lower power consumption.
2Reliability
If impedance calibration is performed to achieve precise impedance matching, then signal distortion is reduced, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The calibration circuit generates multiple types of calibration codes (pull-up calibration code, pull-down calibration code, and correction calibration code) using a unified calibration mechanism. This multi-functional approach enables precise impedance matching for different output conditions without requiring separate calibration circuits, thereby reducing overall device complexity.
Solution Approach 2:
The patent segments the calibration process into distinct code generation stages: pull-up calibration code generation, pull-down calibration code generation, and correction calibration code generation through logic level inversion. This segmentation allows each stage to be optimized independently while maintaining overall system simplicity and reducing circuit complexity.
3Measurement precision
If calibration operation is performed using external reference resistor, then impedance matching accuracy is improved, but manufacturing cost and device area increase
Solution Approach 1:
The patent introduces correction calibration codes as an intermediary element that bridges the calibration process and output signal generation. These correction codes, generated through logic level inversion of pull-up and pull-down calibration codes, enable precise impedance matching without requiring additional external reference resistors or increasing device area.
Data Source
AI summary
A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may generate a calibration code by performing an impedance calibration operation, and may generate a correction calibration code by inverting or maintaining logic levels of the calibration code based on the calibration code. The output circuit may generate an output signal based on an input signal and the correction calibration code.