Output Control Circuit With Cached Latch Timing for Serial Data
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Solution Overview
Problem
In complex data transmission processes, unreasonable logic functions and circuit structures in output control circuits can lead to sequence dislocation, preventing correct data transmission due to limited time redundancy in serial-to-parallel conversion processes.
Innovation Solution
An output control circuit comprising a serial-to-parallel conversion circuit, an intermediate-stage cache circuit, a latch output circuit, and a selection control circuit, which asynchronously converts serial data into parallel data, caches and divides it into categories, and controls latch arrays to output data within extended effective pulse durations, minimizing sequence dislocation and increasing time redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial-to-parallel conversion is performed in a single clock cycle, then conversion speed is improved, but time redundancy is insufficient causing sequence dislocation
Solution Approach 1:
The patent segments the parallel data into multiple categories (first category, second category, etc.) based on their serial-to-parallel conversion sequence. Each category is processed independently through separate latch arrays, allowing different timing control for each group. This segmentation resolves the contradiction by enabling faster conversion while maintaining reliability through categorized timing management.
Solution Approach 2:
The patent performs preliminary classification of parallel data into multiple categories according to their conversion sequence before latching. The selection control circuit pre-determines which latch array will handle each category, preparing the timing control structure in advance. This preliminary action allows the system to achieve high-speed conversion while ensuring each data category has sufficient time redundancy.
2Reliability
If multiple latch arrays are used to process different data categories, then data transmission reliability is improved, but circuit complexity increases
Solution Approach 1:
The patent designs the selection control circuit to universally manage multiple latch arrays through a unified control mechanism. The same selection control logic can handle any number of data categories by dynamically selecting appropriate latch arrays. This multi-functionality approach improves reliability through parallel processing while avoiding proportional increases in overall circuit complexity.
Solution Approach 2:
The selection control circuit acts as an intermediary between the parallel data input and multiple latch arrays. It receives the categorized parallel data and intelligently routes each category to the appropriate latch array based on timing requirements. This intermediary role simplifies the overall circuit architecture by providing a single control point rather than requiring complex direct connections between all components.
3Reliability
If effective pulse duration is extended beyond one clock cycle, then time redundancy is improved reducing sequence dislocation, but circuit response time increases
Solution Approach 1:
The patent implements dynamic timing control where the effective pulse duration for each latch array is adjusted based on its specific category requirements. Different latch arrays can have different pulse durations simultaneously, optimized for their respective data categories. This dynamic approach extends time redundancy where needed while minimizing response time loss in other parts of the circuit.
Solution Approach 2:
The patent applies different timing characteristics to different data categories locally. Each latch array receives customized pulse durations according to its specific timing requirements rather than using a uniform timing approach. This local quality optimization ensures that time redundancy is extended only where necessary to prevent sequence dislocation, while maintaining fast response times for other data paths.
Data Source
AI summary
An output control circuit, a method for transmitting data, and an electronic device are disclosed. The output control circuit includes: a serial-to-parallel conversion circuit configured to obtain at least one group of parallel data through a serial-to-parallel conversion; an intermediate-stage cache circuit configured to divide the at least one group of parallel data into at least two categories of subgroup parallel data according to sequence of serial-to-parallel conversion; a latch output circuit including a plurality of latch arrays each of which receiving any category of subgroup parallel data and latching and outputting any subgroup parallel data in any category of subgroup parallel data; and a selection control circuit configured to, within an effective pulse duration of the any subgroup parallel data, control a latch array for the any subgroup parallel data in the plurality of latch arrays to latch and output the any subgroup parallel data.