Output Circuit Voltage-Withstanding Mechanism for High-Voltage Protection
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Solution Overview
Problem
Integrated circuit output components, such as PMOS and NMOS transistors, are prone to damage due to unstable voltage sources operating at higher voltages, lacking a reliable voltage-withstanding mechanism to prevent damage.
Innovation Solution
Incorporating a voltage-withstanding auxiliary NMOS transistor and auxiliary circuit, which includes a diode and resistor, to provide a resistive effect and current conducting mechanism, ensuring the transistors do not receive excessively high voltages, thereby preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the voltage source operates at higher voltage to increase output capability, then the output power is improved, but the transistor components are damaged due to excessive voltage
Solution Approach 1:
The patent introduces an auxiliary NMOS transistor as an intermediary protective element between the voltage source and the main output transistors. This auxiliary transistor acts as a mediator that limits the voltage reaching the main transistors, allowing the circuit to operate at higher voltages without damaging the components. The auxiliary transistor's gate is connected to a voltage-dividing resistive network that controls its conduction state based on the voltage level, thereby protecting the main transistors while enabling high-voltage operation.
2Device complexity
If no auxiliary voltage-withstanding circuit is used to simplify the design, then the device complexity is reduced, but the components are easily damaged under unstable high voltage conditions
Solution Approach 1:
The patent implements preliminary protective action by pre-configuring the auxiliary NMOS transistor and its associated resistive network before any voltage damage can occur. The voltage-dividing resistors are permanently connected to the gate of the auxiliary transistor, establishing a predetermined voltage threshold for activation. This preliminary setup ensures that when voltage fluctuations occur, the protective mechanism is already in place and can immediately respond to limit excessive voltage reaching the main transistors.
3Reliability
If the auxiliary NMOS transistor is kept conducting to maintain voltage protection, then the voltage-withstanding ability is improved, but the current conduction capability is reduced
Solution Approach 1:
The patent employs dynamic control of the auxiliary NMOS transistor's conduction state through the voltage-dividing resistive network. The resistors create a voltage threshold that dynamically switches the auxiliary transistor between conducting and non-conducting states based on the instantaneous voltage level. When voltage exceeds the threshold, the auxiliary transistor conducts to provide protection; when voltage is within normal range, the auxiliary transistor remains off to avoid impeding current flow. This dynamic behavior allows the circuit to adapt its protection level according to operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the voltage-withstanding ability of the output circuit, reducing the risk of transistor damage by managing voltage variations and maintaining reliable operation even under non-ideal conditions.
Implementation Method 1
the voltage-withstanding auxiliary circuit is configured to provide a current conducting mechanism when the output terminal is operated at a logic high level such that the third gate outputs a current to the voltage source
Implementation Method 2
provide a resistive mechanism when the output terminal is operated at a logic low level such that the third gate has a voltage drop along with the output terminal
Data Source
AI summary
The present disclosure discloses an output circuit having a voltage-withstanding mechanism that includes a PMOS, a NMOS, a voltage-withstanding auxiliary NMOS and a voltage-withstanding auxiliary circuit. The PMOS includes a first source terminal and a first drain terminal coupled to a voltage source and an output terminal and a first gate receiving a first input signal. The NMOS includes a second source terminal and a second drain terminal coupled to a ground terminal and a connection terminal and a second gate receiving a second input signal. The auxiliary NMOS includes a third drain terminal and a third source terminal coupled to the output terminal and the connection terminal. The auxiliary circuit is coupled to the voltage source and a third gate of the auxiliary NMOS and provides a current conducting mechanism and a resistive mechanism respectively when the output terminal is operated at a logic high level and a logic low level.