Output Clock Synchronization to Eliminate Multi-Chip Metastability
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Solution Overview
Problem
High-speed integrated circuits face synchronization challenges due to metastability issues when external synchronization signals transition near internal clock signals, leading to output skew and timing ambiguity, which can prevent systems from meeting timing specifications.
Innovation Solution
The implementation of output interpolative dividers (OID) within each chip dynamically aligns the internal reference clock with the external synchronization signal, ensuring proper setup and hold times and reducing metastability risks by phase-locking the internal clock to the external reference clock, thereby minimizing output/output delay and eliminating the need for re-timing flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronization methods are used, then outputs can be synchronized across multiple integrated circuits, but metastability occurs when the SYNC signal transitions near the internal clock signal, causing timing ambiguity and output skew
Solution Approach 1:
The patent applies preliminary action by capturing the SYNC signal at a predetermined time before it is actually needed for output synchronization. Specifically, the SYNC signal is captured on the falling edge of an internal reference clock, and this captured value is held until the next rising edge of the reference clock when it controls the output. This advance capture ensures that the synchronization signal is ready and stable before required, eliminating timing ambiguity and metastability issues that would occur if capture happened at the last moment.
2Speed
If the SYNC signal is captured at the earliest possible edge, then synchronization speed is maximized, but the capturing circuit enters a metastable state with indeterminate output transition time
Solution Approach 1:
The patent resolves this contradiction by performing the capture action preliminarily - capturing the SYNC signal one clock cycle before it is needed for output control. The captured value is then held stable throughout the subsequent clock cycle. This approach maintains maximum synchronization speed while eliminating the indeterminate transition time associated with metastability, because the capture occurs at a predetermined safe timing point rather than at the earliest possible moment.
Solution Approach 2:
The patent applies the skipping principle by deliberately choosing not to capture the SYNC signal at the earliest possible edge (which would cause metastability), but instead skipping ahead to capture it at a predetermined safe edge of the reference clock. This timing skip ensures that the capture occurs when setup and hold time requirements are guaranteed to be met, avoiding the metastable region entirely while still achieving timely synchronization.
Data Source
AI summary
A chip having output synchronization includes a phase detector for receiving an external reference clock signal, an input delay path coupled to an output of the phase detector and having an output for providing an internal reference clock signal, an output delay path coupled to the output of the input delay path and having an output coupled to a feedback input of the phase detector, a phase adjustment circuit having a first input coupled to the output of the input delay path, a second input for receiving a local clock signal, and an output coupled to the control input of the input delay path, and a synchronization capture circuit having a first input coupled to the output of said input delay path, a second input for receiving the local clock signal, a third input for receiving a synchronization signal, and an output for providing a synchronization trigger signal.