Adaptive Output Clock Phase Control for Jitter Reduction
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Solution Overview
Problem
Adaptive clocking circuits face significant challenges in managing extraneous jitter at the output, which increases noise and affects the performance and power efficiency of digital systems, as existing methods fail to effectively filter or reduce this noise, leading to suboptimal clock signals.
Innovation Solution
A method and circuit that detect transient voltage changes to generate multiple clock phases, select the least noisy phase, and adjust the phase speed of the output clock to match the input clock speed, utilizing a detector circuit, phase selector, and speed controller with logic gates and multiplexers to dynamically adjust the clock frequency and reduce jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a delayed locked loop (DLL) is used to generate clock phases, then clock signal generation is enabled, but extraneous jitter and noise are added to the output clock
Solution Approach 1:
The patent implements dynamic selection of clock phases based on real-time jitter detection. The system continuously monitors the quality of each clock phase from the DLL and dynamically selects the phase with minimum jitter, rather than using a fixed phase selection. This dynamic adaptation resolves the contradiction by maintaining productivity while minimizing harmful jitter through continuous optimization.
Solution Approach 2:
The system changes the parameter of clock phase selection by introducing a jitter metric and selecting phases based on their jitter characteristics. By measuring and comparing jitter parameters of different DLL output phases, the system identifies and selects the optimal phase, thereby reducing the harmful jitter effect while maintaining clock generation functionality.
2Productivity
If the output clock frequency is increased to improve system performance, then processing speed increases, but power consumption increases and jitter becomes more significant
Solution Approach 1:
The patent dynamically adjusts the clock frequency parameter based on detected jitter levels and system conditions. By monitoring the quality of clock phases and adapting the operating frequency accordingly, the system achieves high processing speeds when conditions permit while reducing frequency (and thus power consumption) when jitter becomes problematic, resolving the trade-off between performance and energy efficiency.
3Ease of operation
If traditional shifter circuits are used to select clock phases, then phase selection is achieved, but extraneous jitter cannot be filtered
Solution Approach 1:
The patent implements a feedback mechanism where the jitter of each clock phase is measured and used to control the phase selection process. The shifter circuit is no longer a simple open-loop selector but is controlled by feedback signals indicating the jitter quality of each phase. This feedback loop enables the system to select phases with minimum jitter, thereby filtering out harmful jitter while maintaining ease of phase selection.
Data Source
AI summary
In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.