Output Control Circuit Using Divided Clocks for Timing Precision
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in synchronizing external and internal clock signals accurately, leading to delays and difficulties in generating control signals at precise timing for data output, particularly due to the short period of internal clocks.
Innovation Solution
An output control circuit and output driving circuit are designed to include a period setting signal generation unit, clock division unit, shift unit, and output unit, which generate and process setup signals to produce a divided clock and delayed setup signals, enabling the generation of an output enable reset signal with a precise cycle, thereby securing the operating margin and ensuring accurate data output synchronization with external clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the internal clock period is shortened to increase operating speed, then productivity is improved, but measurement precision of timing control deteriorates
Solution Approach 1:
The patent divides the internal clock signal into multiple divided clock signals with different division ratios (e.g., 2x, 4x, 8x division). This segmentation allows the system to use longer-period divided clocks for timing control operations while maintaining the short internal clock period for high-speed operation, thus resolving the contradiction between productivity and measurement precision.
Solution Approach 2:
The patent introduces divided clock signals as intermediary signals between the internal clock and the timing control logic. These divided clocks serve as mediators that provide sufficient timing margin for control operations without requiring the main internal clock to be slowed down, thereby maintaining both high productivity and precise timing control.
2Productivity
If the internal clock period is shortened, then productivity is improved, but reliability of synchronization deteriorates
Solution Approach 1:
The patent segments the clocking system into multiple hierarchical levels using divided clock signals. This allows synchronization operations to be performed using longer-period divided clocks, providing adequate setup and hold times for reliable synchronization, while the short internal clock period is maintained for high-speed data operations.
Solution Approach 2:
The patent performs timing control and synchronization operations using divided clock signals before the actual high-speed data operations. This preliminary action using slower divided clocks ensures that all timing requirements are met before the fast internal clock begins its critical data transfer operations, thereby ensuring reliability.
3Ease of operation
If timing control is simplified, then ease of operation is improved, but manufacturing precision of timing signals deteriorates
Solution Approach 1:
The patent employs self-service mechanisms where the divided clock signals automatically provide the necessary timing margins and synchronization requirements. The timing control logic simply needs to select appropriate divided clocks based on operation type, and the system self-regulates to maintain precise timing without complex control mechanisms, thus achieving both ease of operation and manufacturing precision.
Data Source
AI summary
An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.