Output Controller Selective Signal Generation for DDR Memory
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing unnecessary current consumption due to the generation of all output enable signals, even when only some are required, which affects the efficiency of data output in high-speed systems like DDR synchronous memory devices.
Innovation Solution
An output controller is designed to generate only the necessary output enable signals based on preset CAS latency, using an output enable signal generator and an output driving signal generator to synchronize data output with the rising and falling edges of the external clock, reducing unnecessary current consumption by activating only the required signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all output enable signals are generated in conventional semiconductor memory devices, then data output timing can be controlled for different CAS latency settings, but unnecessary current consumption increases due to generating signals that are not required
Solution Approach 1:
The patent extracts and removes unnecessary output enable signals from the set of all generated signals. By identifying which signals are actually required based on the specific CAS latency setting and only generating those particular signals, the system eliminates wasted current consumption while preserving the ability to control data output timing for different latency requirements
Solution Approach 2:
Instead of generating all possible output enable signals (excessive action), the patent implements partial action by generating only the specific subset of signals needed for the current CAS latency configuration. This partial generation approach reduces energy consumption while maintaining full adaptability for different timing requirements
2Productivity
If DDR synchronous memory device processes two data bits during one clock cycle, then bandwidth increases by at least two times compared to SDR, but the complexity of data access method increases
Solution Approach 1:
The patent segments the data access method into distinct phases corresponding to rising and falling clock edges. By dividing the single clock cycle processing into two separate half-cycle operations, the system achieves doubled bandwidth while managing complexity through structured segmentation of the access protocol into manageable phases
3Speed
If data output is synchronized with rising and falling edges of external clock, then high-speed operation is achieved, but precise synchronization becomes difficult due to internal processing delay
Solution Approach 1:
The patent implements preliminary action by pre-calculating and pre-positioning output enable signals at appropriate times before the actual data output is needed. This advance preparation compensates for internal processing delays and ensures that data output is precisely synchronized with the rising and falling clock edges, maintaining high-speed operation with accurate timing
Data Source
AI summary
An output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe (CAS) latency, each of the output enable signals having information relating to a delay time from an activation timing of a CAS signal; and an output driving signal generator for receiving the plurality of output enable signals corresponding to the preset CAS latency and outputting rising and falling output driving signals for controlling an output timing of data.