Output Divider Coupling for Synchronized Multi-Clock PLL Signals
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Solution Overview
Problem
Existing clock generators using phase-locked loops with output dividers face challenges in maintaining synchronous frequencies and phases for multiple output clock signals, especially when fractional divider values are involved, due to differing bandwidth and loop characteristics.
Innovation Solution
The solution involves selectively coupling output dividers based on their relationship, either by cascading them when the divider values are integrally related or configuring one divider in parallel with a phase-locked loop and using error correction signals when they are non-integrally related, to align the output clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If distinct phase-locked loops are used for each independently synthesized clock signal, then frequency synthesis flexibility is improved, but phase synchronization between multiple output clock signals deteriorates
Solution Approach 1:
The patent merges multiple independent phase-locked loops into a single shared phase-locked loop system where multiple output dividers are driven by a common reference signal and controlled by a unified control mechanism. This integration ensures that all output clock signals maintain synchronized phases while still allowing independent frequency synthesis through programmable divider values, thus resolving the contradiction between flexibility and synchronization precision.
2Measurement precision
If fractional divider values are used in phase-locked loops, then frequency resolution is improved, but phase relationship stability between multiple clock signals deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the control circuit continuously monitors the phase relationships between multiple output clock signals and dynamically adjusts the divider values to maintain synchronization. This feedback loop compensates for phase drift caused by fractional divider values, allowing high frequency resolution while preserving phase relationship stability across multiple clock outputs.
Data Source
AI summary
A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.