Output Driver Partial Bit De-Emphasis for Signal Integrity
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Solution Overview
Problem
Conventional de-emphasis techniques in digital systems cause signal integrity issues due to asymmetric and full-bit period de-emphasis, leading to degraded signal quality and limited bandwidth.
Innovation Solution
The implementation of partial bit de-emphasis, which allows for adjustable de-emphasis time and amplitude, using a de-emphasis control circuit with a transition detector, variable delay circuit, and leg control circuits to manage the pull-up and pull-down circuits of the output driver, enabling symmetric de-emphasis and improved signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional de-emphasis is applied to compensate for channel loss, then signal amplitude is reduced to counteract capacitive filtering, but signal integrity deteriorates due to asymmetric and full-bit period de-emphasis
Solution Approach 1:
The patent applies partial de-emphasis by controlling the pull-up and pull-down circuits to operate for only a portion of the bit period rather than the full bit period. This partial action reduces the de-emphasis effect on signal amplitude while maintaining enough compensation for capacitive filtering, thereby improving signal integrity without completely sacrificing amplitude compensation
Solution Approach 2:
The patent dynamically adjusts the de-emphasis characteristics by varying the duration of pull-up and pull-down circuit operation within the bit period. The de-emphasis time is made variable rather than fixed, allowing optimization between amplitude compensation and signal integrity maintenance based on channel conditions
2Strength
If full rail-to-rail swing is provided at every bit transition, then signal amplitude is maximized, but subsequent repeated bits are过度 de-emphasized causing amplitude to drop below desired levels
Solution Approach 1:
The patent uses partial bit period de-emphasis to prevent过度 de-emphasis of repeated bits. By limiting the de-emphasis duration to a portion of the bit period rather than the full period, the signal maintains adequate amplitude for repeated bits while still providing sufficient compensation for capacitive effects on transition bits
Solution Approach 2:
The patent employs a control circuit that monitors bit transitions and adjusts the de-emphasis application accordingly. The leg control circuits receive control signals based on detected transitions and adjust the pull-up/pull-down circuit operation to achieve desired amplitude levels for both transition and repeated bits
3Extent of automation
If delay chain is used to implement de-emphasis by sequentially turning on/off pull-up and pull-down circuits, then de-emphasis function is achieved, but output impedance varies dynamically degrading signal integrity
Solution Approach 1:
The patent merges the pull-up and pull-down circuit control into a unified structure where both circuits are controlled simultaneously by coordinated control signals. This simultaneous control maintains constant output impedance while achieving de-emphasis, unlike sequential control that causes impedance variations
Solution Approach 2:
The patent maintains homogeneous (constant) output impedance during de-emphasis operation by ensuring both pull-up and pull-down circuits operate in a coordinated manner. The controlled variation of both circuits together preserves impedance homogeneity, preventing signal integrity degradation
4Device complexity
If asymmetric de-emphasis is applied (strengthening only pull-up or only pull-down), then implementation is simplified, but signal integrity is degraded due to imbalance
Solution Approach 1:
The patent intentionally introduces symmetric asymmetry by applying equal but opposite de-emphasis to both pull-up and pull-down circuits. This symmetric de-emphasis approach balances the effects on both voltage transitions, improving signal integrity while maintaining controlled circuit operation
Solution Approach 2:
The patent uses counterbalancing control where the pull-up and pull-down circuits are controlled in a coordinated, opposite manner. When one circuit is activated for de-emphasis, the other is deactivated or activated correspondingly to maintain balance, preventing the signal integrity issues caused by asymmetric de-emphasis
Data Source
AI summary
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.