Output Driver Tuning Transistor Tri-Stating for Lower DQ Capacitance
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Solution Overview
Problem
High pin capacitance in electronic devices, particularly in high-speed memory devices like DDR3, leads to signal integrity issues due to reflections and increased power consumption, making it challenging to meet tight capacitance specifications at fast speed grades.
Innovation Solution
The method involves tri-stating selected tuning transistors in the ODT and non-ODT legs of the output driver, reducing capacitance on DQ pins without affecting signal speed, allowing for more robust ESD circuit designs by conserving chip real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impedance calibration circuit and ODT circuit are used to control pin impedance, then signal integrity is improved, but pin capacitance increases
Solution Approach 1:
The patent applies dynamics by making the tuning transistors in the ODT circuit controllable and switchable. The transistors can be turned on or off based on operational conditions, allowing the pin capacitance to be dynamically adjusted. This resolves the contradiction by enabling the system to have low capacitance when ODT is not needed while maintaining the ability to provide impedance calibration when required, thus improving signal integrity only when necessary without permanently increasing capacitance.
2Speed
If high pin capacitance is present in high-speed memory devices, then signal transmission capability is improved, but signal reflections increase and power consumption increases
Solution Approach 1:
The patent applies parameter changes by modifying the effective capacitance value of the pin through controlled switching of tuning transistors. By changing the operational state of these transistors, the capacitance parameter can be adjusted to optimal values for different operating conditions. This resolves the contradiction by allowing the system to maintain appropriate capacitance levels for signal transmission while minimizing reflections and power consumption through precise parameter control.
3Reliability
If tuning transistors are kept on to maintain impedance calibration, then impedance control is improved, but pin capacitance increases
Solution Approach 1:
The patent applies periodic action by implementing impedance calibration only when necessary rather than continuously. The tuning transistors are activated periodically or conditionally based on operational requirements, and deactivated when calibration is not needed. This resolves the contradiction by providing impedance control at appropriate intervals while minimizing the time that transistors are on, thus reducing overall capacitance impact and power consumption.
Data Source
AI summary
A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb). A circuit for performing the method includes tri-state components in electrical communication with the tuning transistors, and logic units configured to control the tri-state components. An electronic device includes the output driver having the tri-state components in electrical communication with the logic units.