Output Driver ESD Protection Segmentation
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Solution Overview
Problem
Conventional output driver ICs face challenges in effectively managing electro-static discharge (ESD) events, where surge currents can adversely affect internal components, and existing ESD protection mechanisms may not adequately direct high surge currents away from sensitive areas.
Innovation Solution
The output driver IC incorporates a dual-layer ESD protection system with parallel-connected NMOS transistors, where protection elements with different gate widths are strategically arranged to direct surge currents externally, and a level shifter configuration ensures that protection elements, which also function as drivers, are not overloaded during ESD events by applying floating potentials to their gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single MOS transistor is used as an ESD protection element, then the structure is simple, but the surge current cannot be effectively directed away from sensitive internal components
Solution Approach 1:
The ESD protection element is segmented into multiple parallel-connected MOS transistors with different gate widths. The first MOS transistor has a first gate width and the second MOS transistor has a second gate width that is different from the first gate width. This segmentation allows different transistors to handle different portions of the surge current based on their respective current-carrying capacities, effectively directing surge currents away from sensitive internal components while maintaining a manageable structure.
2Device complexity
If protection elements are used as dual-function elements (driver and protection), then device count is reduced, but the protection element may be overloaded during ESD events
Solution Approach 1:
The patent applies local quality by assigning different gate widths to different MOS transistors based on their specific functions. The first MOS transistor with the first gate width is optimized for normal driver operation, while the second MOS transistor with the larger second gate width is optimized for handling ESD surge currents. This local differentiation ensures that each transistor operates within its designed parameters, preventing overload damage while maintaining dual functionality.
3Reliability
If a larger gate width MOS transistor is used for better ESD protection, then surge current handling is improved, but the transistor occupies more chip area
Solution Approach 1:
Instead of using a single large-gate-width transistor that would occupy excessive chip area, the protection function is segmented across multiple transistors with different gate widths. The first MOS transistor has a smaller gate width suitable for normal operation, while the second MOS transistor has a larger gate width specifically for ESD protection. This segmentation achieves effective surge current handling while optimizing the total chip area occupied by the protection elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the risk of surge currents flowing through protection elements that act as drivers, thereby minimizing the adverse impact of ESD on the IC and enhancing overall protection efficiency.
Implementation Method 1
ESD (electro-static discharge) denotes a discharge of static electricity. If, due to an ESD, an ESD pulse enters an IC, a fault may occur in the IC.
Implementation Method 2
a channel current I1 flows through a channel right under the gate G of the protection element Ma, and simultaneously a channel current I3 flows through a channel right under the gate Gb of the protection element Mb
Data Source
AI summary
An output driver includes a first output signal generator that generates based on a first input signal a first output signal to feed it to the control terminal of a first protection element; a second output signal generator that generates based on a second input signal a second output signal to feed it to the control terminal of a second protection element; and a PN junction structure connected between an output terminal and a power terminal. In normal operation, the first output signal is at low level and the second output signal is at low or high level. When the second input signal is at a floating potential, the first input signal can be at a floating potential regardless of the potential at the power terminal.