Output Driver Circuit Hot-Socket Protection for 3.3 V I/O Pads
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Solution Overview
Problem
Advanced semiconductor process nodes with reduced transistor dimensions cannot support high voltages at input/output pads during hot-socket conditions without experiencing breakdown, as they lack native thick gate field-effect transistors that can handle voltages above 1.8 volts.
Innovation Solution
An output driver circuit in an integrated circuit (IC) is designed with two stacked p-channel and two stacked n-channel field-effect transistors, coupled to an external pad, along with a clamp protection circuit that generates a bias voltage to prevent body diodes of p-channel FETs from becoming forward biased, and multiplexer circuits controlled by a power detector circuit to manage voltages during hot-socket conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced semiconductor process nodes with reduced transistor dimensions are used, then manufacturing precision and integration density are improved, but the ability to support high voltages at input/output pads during hot-socket conditions deteriorates
Solution Approach 1:
The transistor gate is divided into two separate gates (first gate and second gate) stacked vertically. Each gate can be independently controlled, allowing the transistor to handle higher voltages by distributing the voltage stress across multiple gate structures rather than relying on a single thick gate that would be incompatible with advanced process nodes.
Solution Approach 2:
The patent transitions from a planar single-gate structure to a vertical stacked-gate structure. By adding the vertical dimension with multiple gates stacked on top of each other, the device achieves high voltage capability while maintaining compatibility with scaled transistor dimensions in advanced process nodes.
2Reliability
If thick gate field-effect transistors are used to support high voltages above 1.8 volts, then voltage support capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of creating a single complex thick gate structure that would be difficult to manufacture, the patent segments the gate into multiple thinner gates stacked vertically. Each gate layer can be formed using standard fabrication processes compatible with advanced process nodes, avoiding the need for complex thick gate manufacturing.
Solution Approach 2:
Multiple gate structures are merged into a single vertical stack, combining their individual voltage handling capabilities to achieve high overall voltage support. This merged stacked structure provides the equivalent functionality of a single thick gate but with制造 compatibility with advanced process nodes.
3Reliability
If multiple stacked field-effect transistors are used to support high voltages, then voltage support capability is improved, but device complexity increases
Solution Approach 1:
Multiple FETs are merged into a single integrated stacked structure where they share common elements such as the channel region and interconnect structures. This reduces the overall device footprint and simplifies the circuit layout compared to using separate FETs, while maintaining the high voltage support capability.
Solution Approach 2:
The stacked FET structure serves multiple functions simultaneously: it provides high voltage support, maintains compatibility with advanced process nodes, and integrates multiple FET functionalities within a compact structure. The same stacked architecture can be used for both high voltage I/O pads and lower voltage internal circuits.
Data Source
AI summary
An integrated circuit includes an output driver circuit having first and second transistors coupled to an external pad of the integrated circuit and first and second multiplexer circuits. The first multiplexer circuit is configurable to cause the first transistor to be controlled by a first voltage during a data output mode of operation and to couple a first control input of the first transistor to the external pad during a hot-socket protection mode of operation. The second multiplexer circuit is configurable to cause the second transistor to be controlled by a second voltage during the data output mode of operation and to couple a second control input of the second transistor to the external pad during the hot-socket protection mode of operation.