Output Driver Circuit for Low-Skew Pull-Up and Pull-Down Control
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Solution Overview
Problem
Conventional data output drivers experience signal skew due to large load in NOR or NAND gates and slow toggling of PMOS transistors, leading to increased skew in control signals and data output.
Innovation Solution
A data output driver design that reduces the load of the path for generating pull-up and pull-down control signals through NAND combination and simplifies the path by enabling the most significant bit of the ODT calibration circuit, using CMOS inverters and resistors to generate control signals, and includes multiple pre-drivers and drivers to adjust impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NOR gate or NAND gate with large load is used to generate control signals, then the control signals can be generated, but signal skew increases due to slow toggling
Solution Approach 1:
The patent segments the control signal generation into two separate paths: one path generates the enable signal from static signals (enable signal and resistance-adjusting code signal), and another path generates the data signal from the data signal. These two paths are then combined using a NAND gate to produce the final control signal. This segmentation allows each path to be optimized independently, reducing the overall signal skew.
Solution Approach 2:
The patent performs preliminary actions by pre-generating the enable signal and resistance-adjusting code signal separately before combining them. The enable signal is generated in advance from static signals, and the data signal is prepared separately. This preliminary preparation reduces the loading effect on the critical data signal path, thereby reducing signal skew.
2Ease of operation
If enable signal and resistance-adjusting code signal are combined to output control signals, then control signals can be generated, but skew occurs in output data signal
Solution Approach 1:
The patent introduces an intermediary approach by using a two-stage generation process. First, the enable signal is generated as an intermediate signal from static inputs. Second, this enable signal is combined with the data signal through a NAND gate to produce the final control signal. This intermediary step allows the static signals to be processed separately from the dynamic data signal, reducing skew in the output data signal.
3Ease of manufacture
If PMOS transistors are connected in series in NOR gate, then logic function is achieved, but rapid toggling cannot be performed at low power
Solution Approach 1:
The patent inverts the conventional approach by using a NAND gate instead of a NOR gate for combining the enable signal and data signal. The NAND gate structure with PMOS transistors connected in parallel (rather than in series) allows for faster toggling capability while maintaining the required logic function. This inversion of the gate type resolves the toggling speed limitation.
Data Source
AI summary
A data output driver that reduces signal skew includes a data multiplexer which reduces a load of a path through which a pull-up/pull-down control signal is generated by a logic-combination of a data signal. It also decreases the number of bits of a pull-up/pull-down resistance-adjusting code signal, and outputs a data signal in response to high impedance information. Furthermore, a path of an output circuit is simplified through which a pull-up/pull-down control is generated in response to the data signal output from the data multiplexer.