Output Driver Staggering With Process-Sensed Gate Resistance
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Solution Overview
Problem
Existing output driver technologies face challenges in maintaining optimal performance across process variations, as resistance characteristics do not vary with voltage and temperature, leading to suboptimal data rate and noise performance at different process corners and voltages.
Innovation Solution
The implementation of a process-sensing circuit that adjusts the resistance of stagger FETs by selectively bypassing adjustable resistors, using both base and adjustable resistors coupled to the gate of each FET, and incorporating bypass FETs to modify the resistance based on process corners and voltage levels, ensuring optimal performance across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If greater staggering is applied in weak process corner and lower voltages, then noise performance is improved, but data rate deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of staggering resistance by using bypass FETs that can selectively short adjustable resistors based on detected process corner and voltage conditions. The process-sensing circuit dynamically controls the bypass FETs to adjust the effective resistance value, transforming a static resistance system into a dynamic one that adapts to operating conditions. This resolves the contradiction by applying high staggering resistance only when needed (weak corner, low voltage) while maintaining low resistance when speed is critical (strong corner, high voltage).
Solution Approach 2:
The patent changes the resistance parameter of the stagger FETs by using adjustable resistors in series with base resistors, where the adjustable portion can be bypassed by control FETs. The process-sensing circuit detects process corner and voltage level, then controls the bypass FETs to change the effective resistance value. This parameter change allows the system to optimize between noise performance (higher resistance) and data rate (lower resistance) based on actual operating conditions.
2Device complexity
If fixed resistance is used in stagger FETs, then device complexity is reduced, but performance across process variations deteriorates
Solution Approach 1:
The patent segments the resistance control into multiple independent components: base resistors (fixed) and adjustable resistors (controllable via bypass FETs). Each stagger FET gate has its own base resistor and adjustable resistor in series, with a dedicated bypass FET for the adjustable portion. This segmentation allows independent control of resistance values for different FETs and conditions, enabling the system to achieve good performance across process corners while maintaining manageable device complexity through modular structure.
Solution Approach 2:
The process-sensing circuit automatically detects the process corner and voltage level, then autonomously controls the bypass FETs to adjust the resistance values without external intervention. The system serves itself by using its own sensing capabilities to make real-time adjustments, eliminating the need for external calibration or manual configuration. This self-service approach maintains adaptability across process variations while keeping the control structure relatively simple.
Data Source
AI summary
An output buffer includes a first group of stagger FETs coupled in parallel between a power lead and an output signal lead and a second group of stagger FETs coupled in parallel between the output signal lead and a ground lead. Each stagger FET has a gate coupled to a respective base resistor and a respective adjustable resistor. A first group of bypass FETs and a second group of bypass FETs are each coupled across the terminals of a respective adjustable resistor and the gates of the bypass FETs are coupled to either a first process-sensing signal lead or a second process-sensing signal lead.