Output Driver Pulse Alignment With Overlap Feedback Control
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Solution Overview
Problem
High-speed data serialization and transmission circuits using push-pull type drivers face issues with pulse alignment errors leading to degraded timing, reduced output amplitude, increased crow-bar current, and higher power consumption due to overlapping pu-pulses and pd-pulses.
Innovation Solution
A pulse generation and overlap control circuit that includes M clock- and data-controlled pu-pulse and pd-pulse generators, a multi-phase clock generator with a delay-locked loop, and a clock cross-over voltage control circuit to minimize overlap between pu-pulses and pd-pulses using integral and proportional feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If push-pull type drivers are controlled by high-speed pulses in high-speed data serialization circuits, then data transmission speed is improved, but pulse alignment errors cause degraded timing, reduced output amplitude, increased crow-bar current, and increased power consumption
Solution Approach 1:
The patent implements feedback control mechanisms including phase detectors that monitor the alignment between pu-pulses and pd-pulses, and delay-locked loops (DLL) or phase-locked loops (PLL) that automatically adjust clock phase alignment. The system measures overlap between pulses and feeds this information back to correct timing errors, ensuring reliable high-speed operation without manual intervention.
Solution Approach 2:
The patent employs dynamic timing adjustment mechanisms where clock phases are not fixed but can be automatically adjusted in real-time. The delay-locked loop dynamically modifies the phase of clock signals to optimize pulse alignment, and the system can adapt to process, voltage, and temperature variations that affect timing characteristics.
2Productivity
If push-pull type drivers are controlled by high-speed pulses, then data transmission capability is improved, but overlapping pu-pulses and pd-pulses cause increased crow-bar current and power consumption
Solution Approach 1:
The feedback control system continuously monitors for pulse overlap conditions and automatically adjusts clock phases to prevent overlapping pu-pulses and pd-pulses. This eliminates the crow-bar current that occurs when both pull-up and pull-down transistors are simultaneously conductive, thereby reducing power consumption while maintaining high-speed data serialization capability.
Solution Approach 2:
The patent replaces manual or static timing adjustment mechanisms with automated electronic control systems. The delay-locked loop and phase-locked loop use electronic feedback to dynamically adjust timing, replacing what would otherwise require mechanical intervention or fixed timing circuits that cannot adapt to varying operating conditions.
3Device complexity
If manual or static timing adjustment is used for pulse alignment, then device complexity is reduced, but timing accuracy and pulse alignment precision deteriorate
Solution Approach 1:
The patent implements feedback control mechanisms including phase detectors that monitor the alignment between pu-pulses and pd-pulses, and delay-locked loops (DLL) or phase-locked loops (PLL) that automatically adjust clock phase alignment. The system measures overlap between pulses and feeds this information back to correct timing errors, ensuring reliable high-speed operation.
Solution Approach 2:
The timing adjustment system is self-regulating and requires no external intervention. The delay-locked loop automatically acquires and maintains the correct phase relationship between clock signals, and the system can self-correct for timing drift due to process, voltage, or temperature variations without requiring manual calibration.
Data Source
AI summary
The control signal edges of pull-up and pull-down output transistors are aligned by a feedback system. The feedback system works to align the edges of these pull-up and pull-down control pulses while also reducing and/or minimizing any overlap of pull-up and pull-down control pulses. The feedback system uses a proportional feedback loop and an integral feedback loop. The proportional feedback loop controls the crossover voltages of the differential clock signals used to generate the pull-up and pull-down pulses. The integral feedback loop controls the crossover voltages of the differential clock signals output by the delay elements of a delay-locked loop. These crossover voltages are controlled by the feedback loops such that the edges of the pull-down control pulses are aligned to the edges of the pull-up control pulses (and vice versa) without creating excessive overlap.