Output Driver Timing to Prevent Switching Current Damage
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Solution Overview
Problem
Conventional output driving circuits generate large currents when power is on, leading to damage in output copper lines and bonding of output pins, and increased area due to thick gate oxide layers in transistors.
Innovation Solution
The output driving circuit design includes a signal divider, level shifter, inverter, and output driver with P-type and N-type transistors, where the falling time of one driving signal is longer than the other, preventing simultaneous switching and thus reducing large current output, and utilizing a voltage controller to manage voltage levels and transistor states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the P-type transistor and N-type transistor are turned on simultaneously for switching, then the switching function is achieved, but a large current is generated causing damage to output copper lines and bonding
Solution Approach 1:
The patent applies preliminary action by controlling the turning-off sequence of transistors. Specifically, the first transistor (P-type or N-type) is turned off before the second transistor, creating a time gap that prevents simultaneous conduction. This preliminary sequencing of switching actions eliminates the large current spike that would otherwise occur during state transitions, protecting output copper lines and bonding from damage while maintaining reliable switching function.
2Reliability
If thick gate oxide layers are used in transistors to handle high voltage, then voltage handling capability is improved, but the circuit area increases
Solution Approach 1:
The patent applies local quality by differentiating the gate oxide layer thickness based on specific transistor requirements. Transistors that need to handle high voltages (such as those connected to high voltage power sources) are equipped with thick gate oxide layers for reliable voltage handling, while transistors operating at lower voltages use thinner gate oxide layers to minimize area occupation. This localized optimization allows the circuit to achieve necessary voltage handling capability without unnecessarily increasing overall circuit area.
Data Source
AI summary
An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.


