Output Driver Time Lock Loop for Consistent Slew Rates
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Solution Overview
Problem
Integrated circuit output driver circuitry struggles to maintain consistent transition times across a wide range of output loads and varying process, voltage, and temperature conditions, particularly in applications like the Mobile Industry Processor Interface (MIPI) standards, where general-purpose GPIO circuitry fails to meet tight slew rate requirements due to limitations in capacitive feedback and the increasing expense of off-chip calibration.
Innovation Solution
The implementation of feedback circuitry that generates an analog bias voltage to lock output transition time, using a time lock loop apparatus with output driver circuitry and feedback circuitry to adjust pre-driver current sources, ensuring consistent output slew rates across varying loads and conditions without relying on off-chip calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose GPIO circuitry with capacitive feedback is used, then the circuit can operate across a wide range of output loads, but it cannot meet tight transition time requirements
Solution Approach 1:
The patent implements a time lock loop feedback mechanism that continuously monitors the output transition time and adjusts the pre-driver current source accordingly. The feedback circuit compares the actual transition time against a reference and generates correction signals to maintain the desired transition time across varying load conditions, thereby resolving the contradiction between wide load adaptability and tight transition time control.
Solution Approach 2:
The patent dynamically adjusts the pre-driver current source based on real-time transition time measurements. By making the current source adjustable rather than fixed, the system can adapt its driving strength to match the actual load conditions while maintaining consistent transition times, thus achieving both versatility and precision.
2Manufacturing precision
If off-chip calibration is used to achieve accurate delay calibration, then transition time precision is improved, but implementation cost increases
Solution Approach 1:
The patent implements a self-calibrating time lock loop that automatically adjusts and maintains accurate transition times without requiring external off-chip calibration equipment or procedures. The system performs its own calibration internally using on-chip reference circuits and feedback mechanisms, thereby achieving high precision while eliminating the need for expensive off-chip calibration processes.
Solution Approach 2:
The patent extracts the calibration function from external off-chip processes and implements it entirely within the chip using on-chip reference circuits and feedback mechanisms. By taking out the dependency on external calibration equipment and performing calibration internally, the system achieves accurate delay calibration without the associated implementation costs.
3Manufacturing precision
If off-chip calibration techniques are used, then accurate delay calibration can be achieved, but they are not effective for very wide variations in output load capacitance
Solution Approach 1:
The patent implements a dynamic time lock loop feedback system that continuously adapts to varying load capacitance conditions. The feedback mechanism monitors transition times in real-time and adjusts the pre-driver current source dynamically, enabling the system to maintain accurate calibration across very wide variations in output load capacitance that static off-chip calibration techniques cannot handle.
Solution Approach 2:
The patent performs preliminary calibration actions continuously through the feedback loop, adjusting the pre-driver current source in advance of load changes to maintain accurate transition times. This continuous preliminary adjustment capability allows the system to handle very wide variations in output load capacitance effectively.
Data Source
AI summary
Output driver feedback circuitry limits output slew rates across a wide range of output loads. A transition time lock loop architecture of the feedback circuitry compares a transition time pulse with a reference pulse to adjusts transition time of an output signal for various process-voltage-temperature (PVT) process corners, output voltage domains and output capacitances. Reference pulse generation circuitry provides a reference pulse in phase with the transition time pulse for each rise and fall of the output signal.