Output Driver Tuning Transistor Tri-Stating for Lower Pin Capacitance
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Solution Overview
Problem
High pin capacitance in electronic devices, particularly in high-speed memory devices like DDR memory devices, leads to signal integrity issues and increased power consumption, making it challenging to meet tight capacitance specifications at fast speed grades.
Innovation Solution
The method involves tri-stating selected tuning transistors in the ODT and non-ODT legs of the output driver in an input/output circuit, reducing pin capacitance without affecting signal speed, thereby allowing more robust designs such as improved ESD circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impedance calibration circuits and ODT circuits are used to control pin impedance, then pin impedance can be adjusted to match device impedance, but pin capacitance increases which adversely affects signal integrity and power consumption
Solution Approach 1:
The patent applies dynamics by making the tuning transistors in the ODT circuit controllable and switchable. The circuit dynamically adjusts between different states: during read operations, the tuning transistors are activated to provide impedance matching; during non-read operations, they are deactivated to reduce pin capacitance. This temporal differentiation allows the same circuit to serve multiple functions at different times, resolving the contradiction between maintaining signal integrity and reducing capacitance.
Solution Approach 2:
The patent changes the operational parameters of the ODT circuit by controlling the activation state of tuning transistors based on operation type. During read operations, the circuit parameter (impedance matching) is optimized; during non-read operations, the circuit parameter (capacitance) is minimized. This parameter switching allows the system to adapt to different operational requirements, resolving the contradiction between signal integrity and capacitance reduction.
2Quantity of substance
If tuning transistors in ODT circuits are turned off during default operational state to reduce pin capacitance, then pin capacitance decreases improving signal integrity, but signal transmission speed may be affected
Solution Approach 1:
The patent uses dynamics to selectively activate tuning transistors only when needed for read operations. During non-read operations, the transistors remain off to minimize capacitance. This dynamic control ensures that signal transmission speed is maintained during read operations when transistors are active, while capacitance is reduced during other operations when transistors are inactive, thus resolving the contradiction between speed and capacitance.
Solution Approach 2:
The patent changes the operational state of tuning transistors based on the type of operation being performed. During read operations, the transistors are in an active state to maintain signal transmission speed; during non-read operations, they are in an inactive state to reduce pin capacitance. This conditional parameter change resolves the contradiction by optimizing for the appropriate parameter depending on the operational context.
3Speed
If all tuning transistors remain active to maintain signal transmission speed, then signal speed is preserved, but pin capacitance increases reducing data valid window and increasing power consumption
Solution Approach 1:
The patent applies dynamics by controlling the activation state of tuning transistors based on operational requirements. During read operations, transistors are active to maintain signal speed; during non-read operations, they are inactive to reduce power consumption and capacitance. This dynamic control resolves the contradiction between maintaining signal speed and reducing power consumption by activating components only when necessary.
Solution Approach 2:
The patent changes the operational parameter of tuning transistors from always-on to conditionally-on based on operation type. During read operations, the parameter (transistor activation) is set to maintain signal speed; during non-read operations, it is set to minimize power consumption and capacitance. This parameter switching resolves the contradiction between speed and power consumption.
Data Source
AI summary
A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb). A circuit for performing the method includes tri-state components in electrical communication with the tuning transistors, and logic units configured to control the tri-state components. An electronic device includes the output driver having the tri-state components in electrical communication with the logic units.