Output-Gated Scan Flip-Flops for Low-Power IC Testing
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Solution Overview
Problem
Scan-based testing in integrated circuit devices leads to high power consumption and localized voltage drops (IR drop) due to frequent state changes at data output terminals, causing timing violations and scan test failures.
Innovation Solution
Implementing output-gated scan flip-flop circuits that suppress data output signals during the scan shift phase based on deterministic settling of input signals, reducing unnecessary state changes and current flow through resistive interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-based testing is performed with traditional flip-flop circuits, then test coverage and defect detection capability are improved, but dynamic power consumption and localized IR drop increase due to frequent state changes at data output terminals
Solution Approach 1:
The patent extracts the data output signal path from the flip-flop circuit by introducing an output gating logic that selectively suppresses the data output signal during scan shift phase. This separation allows the scan chain to operate independently without driving the data output terminals, thereby reducing dynamic power consumption and IR drop while maintaining test coverage through the scan output terminal.
Solution Approach 2:
The patent introduces dynamic control of the flip-flop output through a scan enable signal that switches between capture mode and scan shift mode. During scan shift phase, the output gating logic dynamically suppresses the data output signal based on the scan enable state, allowing the circuit to adapt its behavior to minimize power consumption during testing while maintaining functional operation during normal modes.
2Reliability
If scan-based testing is performed with traditional flip-flop circuits, then test coverage and defect detection capability are improved, but localized voltage drops (IR drop) increase causing timing violations and scan test failures
Solution Approach 1:
The patent extracts the data output signal path from the flip-flop circuit by introducing an output gating logic that selectively suppresses the data output signal during scan shift phase. This separation allows the scan chain to operate independently without driving the data output terminals, thereby reducing dynamic power consumption and IR drop while maintaining test coverage through the scan output terminal.
3Use of energy by moving object
If output gating logic is added to suppress data output signals during scan shift phase, then dynamic power consumption and IR drop are reduced, but device complexity increases
Solution Approach 1:
The output gating logic is designed to serve multiple functions: it suppresses the data output signal during scan shift phase to reduce power consumption, while simultaneously allowing the data output signal to pass through during capture mode for functional operation. This multi-functionality is achieved by controlling the gating logic with the existing scan enable signal, eliminating the need for separate control circuits and minimizing the increase in device complexity.
4Use of energy by moving object
If output gating logic is added to suppress data output signals during scan shift phase, then dynamic power consumption and IR drop are reduced, but test time may increase due to additional control requirements
Solution Approach 1:
The output gating logic is designed to serve multiple functions: it suppresses the data output signal during scan shift phase to reduce power consumption, while simultaneously allowing the data output signal to pass through during capture mode for functional operation. This multi-functionality is achieved by controlling the gating logic with the existing scan enable signal, eliminating the need for separate control circuits and minimizing the increase in device complexity.
Data Source
AI summary
In an example, a flip-flop (FF) circuit includes a data output terminal and data selection logic that can be configured to output one of a scan data input signal or a functional data input signal as a selected data signal based on a scan enable signal. The FF circuit further includes a data storage circuit that can be configured to capture and store a logic value represented by the selected data signal as a stored logical value. The FF circuit further includes output gating logic that can be coupled to the data output terminal and is configured to generate a data output signal at the data output terminal based on the stored logical value during a capture phase of a scan mode of operation. During a scan shift phase of the scan mode of operation, the output gating logic suppresses the data output signal at the data output terminal.