Output Stage DC Offset Control for Power Dissipation Balance

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Solution Overview

Problem

Existing output stages with push-pull arrangements face inefficiencies due to unequal power dissipation in transistors handling asymmetrical drive signals, leading to suboptimal energy management and increased power loss.

Innovation Solution

A system that includes a phase splitter, DC offset signal generator, adder, subtractor, and combiner to equalize power dissipation in drive transistors by generating and applying a DC offset signal, ensuring balanced power handling across both transistors, and utilizing a transformer for signal combination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a push-pull output stage handles asymmetrical drive signals, then the output signal can represent amplified versions of the drive signal, but unequal power dissipation occurs in the transistors leading to increased power loss

Engineering Contradiction:
Improvepower dissipation balanceVSAvoidpower loss
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The patent applies asymmetry by introducing a DC offset signal that is added to one transistor's drive signal and subtracted from the other's, creating unequal drive conditions that compensate for the inherent asymmetry in power dissipation. This deliberate asymmetric adjustment balances the power distribution between transistors handling asymmetrical drive signals

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the parameter of drive signal voltage by superimposing a DC offset component. The DC offset signal generator produces a voltage that shifts the operating point of the transistors, thereby adjusting their power dissipation characteristics to achieve balance while maintaining signal amplification functionality

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If the cross-over point is not optimized, then the output stage can operate with simple drive signals, but total power dissipation increases due to unbalanced power handling

Engineering Contradiction:
Improvetotal power dissipationVSAvoidsignal processing complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the drive signal processing by separating the AC drive signal from the DC offset component. The DC offset signal generator independently produces a correction signal that is then combined with the main drive signal through adder and subtractor circuits, allowing independent optimization of power balance without redesigning the entire signal path

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The DC offset signal acts as an intermediary element that mediates between the asymmetrical drive signals and the transistors. By introducing this intermediate DC component, the patent enables power dissipation balancing without directly modifying the original drive signal waveform or requiring complex feedback control

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes total power dissipation in the output stage by dynamically adjusting the DC offset to balance the power handled by each transistor, enhancing efficiency and reducing energy loss.

Implementation Method 1

a combiner for combining the first and second output signals to generate a phase combined output signal

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS9548700B2Control of cross-over point
Publication Date: 2017.01.17 SNAPTRACK INC
  • US9548700B2 patent drawing
  • US9548700B2 patent drawing
  • US9548700B2 patent drawing

AI summary

There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal.