Output Stage Slew Rate Calibration for Stable Driving Voltage
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Solution Overview
Problem
Conventional output stages in chips face challenges in maintaining accurate slew rate and voltage level due to varying loads, leading to waveform distortion and reduced operational speed, as they rely on non-ideal inverters with parasitic capacitances and on-resistances that affect transition times.
Innovation Solution
An output stage comprising a first and second switching current module, a switching capacitor module, a calibrating control circuit, and a time constant calibrating circuit that generates a reference slew rate, allowing for calibration of currents and capacitances to match the reference slew rate, combined with a voltage clamper to set high/low voltage ranges and limit amplitude, ensuring stable slew rate and voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sizes of inverters are increased to reduce voltage differences between loads and programmable regulators, then voltage level accuracy is improved, but parasitic capacitances are magnified such that operative speed is lowered
Solution Approach 1:
The patent changes the control parameter from inverter size to a dedicated slew rate control circuit that directly regulates the current charging/discharging the load capacitance. By controlling the current magnitude rather than relying on fixed inverter sizes, the system achieves accurate voltage levels without the parasitic capacitance penalty of large inverters.
Solution Approach 2:
The patent segments the voltage control function into separate components: programmable regulators for setting voltage levels and a dedicated slew rate control circuit for managing transition speed. This separation allows independent optimization of voltage accuracy and operative speed without the trade-off inherent in using oversized inverters for both functions.
2Measurement precision
If the sizes of inverters are increased to reduce voltage differences, then voltage level accuracy is improved, but waveform distortion occurs due to non-linear effects from on-resistances
Solution Approach 1:
The patent transitions from using inverter on-resistances as the control mechanism to using a dedicated current source that provides linear current control. This current source, controlled by the slew rate control circuit, charges and discharges the load capacitance in a linear fashion, eliminating the non-linear waveform distortion caused by inverter on-resistances while maintaining accurate voltage levels.
Solution Approach 2:
The patent introduces a current source as an intermediary between the control logic and the load capacitance. This current source acts as a buffer that provides linear current delivery independent of the inverter characteristics, thereby eliminating the non-linear effects of inverter on-resistances while maintaining the ability to control voltage levels accurately.
3Speed
If dead time of PMOS and NMOS is controlled to adjust slew rate, then transition time is adjusted, but waveform distortion occurs
Solution Approach 1:
The patent extracts the slew rate control function from the dead time control mechanism of the PMOS and NMOS switches. By separating these functions and implementing dedicated slew rate control through current magnitude regulation, the system achieves transition time control without the waveform distortion that results from dead time adjustments.
Solution Approach 2:
The patent changes the control parameter for slew rate from dead time duration to current magnitude. By controlling the amount of current charging and discharging the load capacitance, the system achieves precise transition time control while maintaining linear voltage transitions and avoiding the waveform distortion associated with dead time control.
4Speed
If parallel inverters are arranged to adjust on-resistances and change slew rate, then transition time is adjusted, but voltage differences occur when loads vary
Solution Approach 1:
The patent implements dynamic current control through the slew rate control circuit, which can adjust the magnitude of current charging and discharging the load capacitance in real-time. This dynamic control allows the system to maintain accurate voltage levels and consistent slew rate regardless of load variations, overcoming the static limitations of fixed inverter arrangements.
Solution Approach 2:
The patent incorporates feedback mechanisms in the slew rate control circuit that monitor the actual voltage levels and transition rates, then adjust the current magnitude accordingly. This feedback control ensures that voltage level accuracy is maintained and slew rate is precisely controlled even when loads vary, eliminating the voltage differences that occur with fixed inverter arrangements.
Data Source
AI summary
An output stage configured to control a driving voltage thereof is provided. The output stage includes: a first switching current module, coupled to a node for outputting a first current; a second switching current module, coupled to the node for outputting a second current; a switching capacitor module with a capacitance, coupled to the node; a calibrating control circuit, for calibrating the first current, the second current and the capacitance; a time constant calibrating circuit, for generating a reference slew rate, and controlling the calibrating control circuit to selectively calibrate the first current, the second current and the capacitance, such that a ratio of the first current and the capacitance and the ratio of the second current and the capacitance conform to the reference slew rate; and a voltage clamper for setting a high/low voltage range and limiting a amplitude of the driving voltage within the high/low voltage range.