Output Transistor Gate Decoupling for EMC Robustness
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Solution Overview
Problem
Existing solutions for enhancing Electro-Magnetic Compatibility (EMC) robustness in sensor output signals require either extra bond pads and external passive components or large integrated capacitors, which lead to power management losses and temperature-dependent voltage drift, affecting sensor parameter stability.
Innovation Solution
An output circuit design that includes an output transistor with an inherent storage capacitor, a gate switch to decouple the transistor gate from other components during supply voltage decreases, and a reset controller to maintain a defined reset time, eliminating the need for separate capacitors and ensuring low leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external storage capacitor is used to supply the IC during EMC pulses, then EMC robustness is enhanced, but an extra bond pad and external passive component are required
Solution Approach 1:
The patent merges the function of the external storage capacitor with the intrinsic gate capacitance of the output transistor. Instead of using a separate external capacitor, the gate capacitance of the output transistor itself is utilized to maintain the output state during supply voltage drops, thereby eliminating the need for external passive components while maintaining EMC robustness
Solution Approach 2:
The output transistor's own gate capacitance is used to serve the function of a separate storage capacitor. The gate capacitance naturally holds the charge required to maintain the output state during EMC disturbances, making the system self-sufficient without requiring additional external components
2Reliability
If a relatively large integrated capacitor is used to supply output circuitry, then EMC robustness is improved, but power management loss occurs and temperature-dependent voltage drift affects sensor parameter stability
Solution Approach 1:
The patent combines the storage function with the gate structure of the output transistor. The gate capacitance inherently provides the necessary charge storage without requiring a separate large integrated capacitor, thereby eliminating power management losses associated with charging and discharging large capacitors while maintaining temperature stability
Solution Approach 2:
The patent changes the approach from using a large capacitor with high capacitance value to utilizing the small but sufficient gate capacitance of the transistor. This parameter change eliminates the energy losses and temperature-dependent voltage drift issues associated with large integrated capacitors while maintaining the necessary charge storage capability
3Reliability
If a relatively large integrated capacitor is used to supply output circuitry, then EMC robustness is improved, but the capacitor discharges slowly at lower temperatures when power is switched off
Solution Approach 1:
The patent merges the storage function with the gate structure, using the transistor's gate capacitance instead of a separate large capacitor. This eliminates the temperature-dependent discharge time issue because the gate capacitance is small and can be quickly discharged through the switch when power is turned off, regardless of temperature
Solution Approach 2:
The patent introduces a switch that dynamically controls the discharge path of the gate capacitance. When power is switched off, the switch provides a low-impedance discharge path that quickly releases the stored charge in the gate capacitance, preventing slow discharge at low temperatures and ensuring rapid reset of the output state
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances EMC robustness by maintaining the output signal state during disturbances and ensuring predictable behavior across temperatures without the need for area-consuming passive components, maintaining Class A functionality and providing a guaranteed reset time.
Implementation Method 1
When the gate of the output transistor is decoupled, a charge at the gate is maintained in a capacitor inherent within the gate of the output transistor
Data Source
AI summary
An output circuit including an output transistor configured to provide an output signal; and a gate switch configured to decouple a gate of the output transistor from other components of the output circuit when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor is decoupled, a charge at the gate is maintained in a capacitor inherent within the gate of the output transistor.