Outstanding Load Miss Buffer for Out-of-Order Data Hazard Resolution
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Solution Overview
Problem
Load store units face challenges in reissuing missed load instructions without causing data hazards, particularly when instructions are issued out of order, leading to complications in tracking and resolving potential data hazards.
Innovation Solution
The implementation of a load store unit with an outstanding load miss buffer and a load miss result buffer allows missed load instructions to be stored and reissued without relying on extensive tracking systems, by grouping dependent instructions and retrieving data from the load miss result buffer instead of the level one cache, thereby eliminating data hazards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load instructions are issued out of order to improve performance, then productivity is improved, but data hazards may occur leading to reliability deterioration
Solution Approach 1:
The patent introduces an intermediary buffer system between the out-of-order issue mechanism and the in-order execution requirements. The load buffer stores load instructions with their original program order tags, allowing them to be issued out of order for performance while maintaining the ability to detect and resolve data hazards by comparing against the stored order information.
Solution Approach 2:
The patent implements feedback mechanisms where the load buffer continuously monitors the order of issued load instructions and compares it with the original program order. When a data hazard is detected (a later load instruction being issued before an earlier one that it depends on), the system feedbacks control signals to stall or reorder execution, ensuring reliability while allowing out-of-order issuance for performance.
2Reliability
If extensive tracking systems are implemented to prevent data hazards, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential tracking information (load instruction order and dependency relationships) from the complex execution flow and stores it compactly in the load buffer. This selective extraction of critical tracking data simplifies the overall system by focusing only on the necessary information needed for hazard detection, rather than implementing comprehensive tracking of all instruction states.
Solution Approach 2:
The patent creates simplified copies of load instruction metadata (program counter, original order tag, dependency information) in the load buffer. These copies serve as lightweight tracking records that enable hazard detection without requiring complex real-time analysis of the full instruction stream, reducing device complexity while maintaining reliability.
3Productivity
If load instructions are stored in buffer to allow out-of-order issuance, then productivity is improved, but loss of time occurs due to buffer management overhead
Solution Approach 1:
The patent performs preliminary actions by pre-storing load instruction metadata (program counter, original order, dependency information) in the load buffer at the time of instruction fetch, before execution is needed. This preliminary organization of information allows for rapid hazard checking and out-of-order issuance decisions, reducing the time loss associated with buffer management during critical execution paths.
Data Source
AI summary
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.