Oval Bit Line Contact Plugs for Semiconductor Integration
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Solution Overview
Problem
In highly integrated semiconductor devices, the proximity of bit line contact plugs and storage node contact plugs increases the likelihood of electrical shorts due to their close proximity, which is exacerbated by the miniaturization of bit line contact plugs beyond the resolution limits of photolithography processes.
Innovation Solution
The semiconductor device design incorporates bit line contact plugs with longish shapes, specifically oval shapes parallel to the bit lines, formed by creating circle-shaped contact holes and isotropically etching them to enlarge in a specific direction, using a combination of anisotropic and isotropic etch processes with different etch rates for various insulation layers, to increase the distance between bit line and storage node contact plugs and enhance contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit line contact plugs are miniaturized to achieve higher integration, then device integration is improved, but the probability of electrical shorts between bit line contact plugs and storage node contact plugs increases
Solution Approach 1:
The bit line contact plug is designed with an asymmetric longish shape having a major axis and a minor axis, where the major axis dimension is greater than the minor axis dimension. This asymmetric geometry allows the contact plug to extend preferentially in one direction, increasing the distance to adjacent storage node contact plugs and reducing electrical short probability while maintaining compact cell area.
Solution Approach 2:
The invention transitions from considering only the minor axis dimension of the contact plug to utilizing both major and minor axes dimensions. By controlling the etch process to create an elongated shape with a major axis, the design effectively uses dimensional orientation to increase spacing in critical directions while maintaining overall compactness.
2Area of stationary object
If bit line contact plugs are made smaller to reduce cell area, then area efficiency is improved, but photolithography resolution requirements become more difficult to meet
Solution Approach 1:
The contact hole shape is predetermined and controlled during the etching process itself, rather than relying solely on photolithography patterning. By using anisotropic etching to create the longish shape from a circular contact hole, the final dimensions are determined by etch control rather than photolithography resolution, relaxing the photolithography requirements.
Solution Approach 2:
The invention replaces reliance on photolithography mechanical patterning with a chemical etching process to define the final contact plug shape. The anisotropic etch process substitutes for the photolithography step in determining the critical dimensions, allowing more precise control independent of optical resolution limits.
3Area of stationary object
If bit line contact plugs are positioned closer to storage node contact plugs to increase integration density, then area efficiency is improved, but electrical short probability increases
Solution Approach 1:
The contact plug is designed with non-uniform dimensions, having a major axis dimension that is larger than the minor axis dimension. This local variation in size allows the contact plug to occupy space efficiently in one direction (minor axis) while extending in another direction (major axis) to maintain distance from storage node contact plugs, achieving both density and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the probability of electrical shorts and minimizes contact resistance by increasing the distance between bit line and storage node contact plugs while maintaining efficient fabrication within the limitations of current photolithography techniques.
Implementation Method 1
The second insulation layer is isotropically etched to enlarge the contact hole in a second direction substantially perpendicular to the first direction
Implementation Method 2
The first insulation patterns may have a different etch rate from the second insulation layer while the second insulation layer is isotropically etched
Data Source
AI summary
A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.