Oval-Shaped Contact for Non-Volatile Memory Misalignment
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Solution Overview
Problem
In non-volatile memory (NVM) devices, misalignment of contacts between adjacent gate stacks can lead to voltage breakdown due to a thin dielectric layer, causing shorts between the contact and the gate stack, especially during programming and erasing operations.
Innovation Solution
The contact between gate stacks is designed with an oval shape, where the lateral dimension is thinner and the orthogonal dimension is thicker, providing increased misalignment tolerance and preventing shorts by maintaining equivalent conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the contact is placed closer to the gate stack to save space, then the device density is improved, but the risk of voltage breakdown and shorting increases due to the thin dielectric layer
Solution Approach 1:
The contact structure employs an asymmetric design where the contact opening is offset from the center of the common source/drain region toward one gate stack. This asymmetric positioning strategically places the contact closer to one gate while maintaining adequate spacing from the other, thereby improving device density without proportionally increasing the risk of voltage breakdown across both gates.
Solution Approach 2:
The dielectric layer exhibits local quality variations with different thicknesses in different regions. The dielectric is thicker in regions closer to the gates and thinner in the center, allowing the contact to be positioned in the thinner region to save space while the thicker regions provide enhanced protection against voltage breakdown.
2Reliability
If the gate stacks are placed further apart to prevent shorting, then the reliability is improved, but the device density deteriorates
Solution Approach 1:
Instead of symmetrically spacing gate stacks equidistantly from the contact, the design uses asymmetric gate stacking where one gate is closer to the contact than the other. This allows the gate stacks to be positioned closer together overall while maintaining adequate electrical isolation, thereby improving device density without compromising reliability.
Solution Approach 2:
The patent introduces vertical dimensionality by stacking multiple gates at different heights and positions. This three-dimensional gate arrangement allows for closer horizontal spacing of gate stacks while maintaining electrical isolation through vertical separation, thus improving device density without increasing shorting risk.
3Ease of manufacture
If a circular contact is used, then the manufacturing is simpler, but the misalignment tolerance is reduced
Solution Approach 1:
The contact opening transitions from a symmetric circular shape to an asymmetric elongated or rectangular shape. This asymmetric contact geometry provides greater dimensional tolerance in the direction parallel to the gate stacks, allowing for larger alignment margins during manufacturing while maintaining simple fabrication processes.
Solution Approach 2:
The contact dimensions are optimized by changing the shape parameters from a circle to an elongated form with specific aspect ratios. This parameter change increases the contact's tolerance to misalignment in critical directions while maintaining manufacturability through standard photolithography processes.
Data Source
AI summary
A semiconductor device is disclosed that comprises a first non-volatile memory cell, a second non-volatile memory cell, an active region between the first and second memory cells, and an electrically conductive contact touching the active region, wherein the contact has a horizontal cross-section that is at least five percent smaller in a first dimension than in a second dimension.