Automated Debugging for Over-Constrained Circuit Verification
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Solution Overview
Problem
In the electronic chip design industry, over-constrained circuit verification environments occur due to logically flawed or overly strict constraints, leading to unexpected results and difficulties in detecting and debugging such situations, as formal analysis tools cannot satisfy conflicting constraints, resulting in truncated execution paths and failure to report assertion failures.
Innovation Solution
An automated method is provided to detect and debug over-constrained situations by identifying a minimum subset of constraints that cause an over-constrained event, using techniques like cover checks and vacuity checks, and determining whether constraints are realizable, thereby isolating the cause of the over-constrained situation and providing information on the minimum subset of constraints and their design fan-in.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal analysis tools apply overly strict or conflicting constraints to verify circuit designs, then verification completeness is improved, but the verification process becomes over-constrained and fails to produce meaningful results
Solution Approach 1:
The patent segments the constraint set into individual constraints and systematically tests each constraint to identify which ones cause over-constrained conditions. The formal analysis tool divides the verification problem into manageable parts by isolating conflicting constraints, allowing designers to understand and fix specific issues rather than dealing with the entire constraint set at once.
Solution Approach 2:
The patent changes the parameters of constraint verification by introducing new metrics such as constraint conflict detection, over-constrained event identification, and minimum subset analysis. These parameter changes enable the tool to measure and report on the health of the verification environment, transforming an opaque failure state into a diagnosable condition.
2Measurement precision
If formal analysis tools use comprehensive constraint sets to ensure thorough verification, then assertion coverage is improved, but the tool cannot satisfy conflicting constraints and reports false passing results
Solution Approach 1:
The patent performs preliminary analysis of constraints before executing the full formal verification. The tool pre-checks constraints for conflicts, identifies over-constrained events in advance, and reports potential issues before they affect the verification results. This preliminary action prevents false passing results by detecting constraint problems upfront.
Solution Approach 2:
The patent implements feedback mechanisms that monitor the verification process and detect when constraints become over-constrained. The tool provides continuous feedback about constraint satisfaction, identifies conflicting constraints, and alerts designers when the verification environment becomes invalid. This feedback loop ensures result accuracy by preventing misleading passing results.
3Adaptability or versatility
If formal analysis tools apply multiple strict constraints simultaneously, then verification scope is improved, but the execution paths become truncated and the tool cannot explore the design adequately
Solution Approach 1:
The patent extracts and isolates the minimum subset of constraints that cause over-constrained conditions. By taking out only the problematic constraints from the full constraint set, the tool reduces complexity while maintaining verification scope. Designers can focus on removing or modifying just the essential conflicting constraints rather than managing the entire constraint set.
Data Source
AI summary
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.