Over-Under IC Interconnect Layout for Noise Isolation
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Solution Overview
Problem
The increasing number of interconnects on integrated circuits (ICs) leads to delays and unwanted noise, affecting performance and power efficiency, as existing designs often place signaling and power/ground interconnects on the same side of the chip, limiting their separation and optimization.
Innovation Solution
The solution involves creating over and under interconnects by placing power/ground interconnects on one side of the chip assembly and signaling interconnects on the opposing side, utilizing techniques such as capacitive coupling and active interposers to manage signal routing and power delivery, while integrating massive capacitors and heat spreaders for thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If signaling interconnects and power/ground interconnects are placed on the same side of the chip, then the layout is simpler and manufacturing is easier, but noise increases and performance deteriorates due to interference between high-speed signaling and low-speed power/ground signals
Solution Approach 1:
The patent applies dimensionality change by moving power/ground interconnects to the backside of the chip while keeping signaling interconnects on the front side. This spatial separation in the third dimension (depth/layer) eliminates interference between high-speed signaling and low-speed power/ground signals, resolving the noise problem while maintaining manufacturing feasibility through standard flip-chip or substrate mounting techniques.
Solution Approach 2:
The patent segments the interconnect system into two distinct groups: signaling interconnects on the front side and power/ground interconnects on the back side. This segmentation separates high-speed data transmission paths from low-speed power delivery paths, preventing cross-talk and noise coupling while allowing each interconnect type to be optimized independently for its specific function.
2Adaptability or versatility
If more interconnects are used to connect increasing numbers of electronic circuits, then connectivity and functionality improve, but signal delay increases and power efficiency deteriorates
Solution Approach 1:
By transitioning to 3D integration with interconnects on both sides of the chip, the patent reduces signal path lengths through vertical connections (via holes, TSVs) rather than lateral routing. This dimensional change enables shorter, more direct signal paths that reduce delay while accommodating increased connectivity density.
Solution Approach 2:
The patent introduces an intermediary substrate or interposer that facilitates connections between multiple chips and circuits. This intermediary provides optimized routing paths and reduces the number of interconnect hops required, thereby decreasing cumulative signal delay while enabling complex multi-chip systems with high connectivity.
3Adaptability or versatility
If more interconnects are used to support increased circuit density, then functionality improves, but unwanted noise and interference increase, reducing power efficiency
Solution Approach 1:
The patent segments power delivery and signal transmission into separate physical domains (front side for signaling, back side for power/ground). This segmentation allows independent optimization of each system, enabling low-impedance power paths with sufficient current capacity for high-density circuits while keeping signaling paths isolated from power-related noise, thus maintaining power efficiency.
Solution Approach 2:
By utilizing the backside of the chip for power/ground interconnects, the patent creates dedicated power delivery paths that are physically separated from signal paths. This dimensional separation reduces electromagnetic coupling and noise interference, allowing high-density circuits to operate with better power efficiency and reduced energy loss to noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces noise and enhances performance by separating low-speed power/ground signals from high-speed signaling, improving power efficiency and thermal contact, thereby optimizing IC performance and reducing signal delays.
Implementation Method 1
utilizing techniques such as capacitive coupling and active interposers to manage signal routing and power delivery
Implementation Method 2
integrating massive capacitors and heat spreaders for thermal management
Data Source
AI summary
Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.