Overclocking via Sleep Mode and ACPI

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Solution Overview

Problem

Conventional computer system overclocking methods either waste time due to rebooting in static overclocking or result in unstable systems due to non-optimum clock rate adjustments in dynamic overclocking.

Innovation Solution

Implementing an overclocking method that uses ACPI to set and adjust operating voltage and clock rate, allowing the system to enter a sleep mode and resume, thereby bypassing the reboot process and optimizing memory controller parameters for stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If static overclocking process is used to adjust operating voltage and clock rate, then the system stability is improved, but the time consumption increases due to rebooting

Engineering Contradiction:
Improvesystem stabilityVSAvoidtime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by entering sleep mode before overclocking and using ACPI to pre-configure the memory controller parameters. This allows the system to resume from sleep mode with the overclocking settings already in place, eliminating the need for full reboot and reducing time consumption while maintaining stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the state parameter from full system reboot to sleep mode transition. By utilizing ACPI and modifying memory controller parameters during the sleep-resume cycle rather than requiring a complete reboot, the system achieves parameter changes with reduced time loss.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If dynamic overclocking process is used to adjust clock rate without rebooting, then the time consumption is reduced, but the system stability deteriorates due to non-optimum clock rate adjustments

Engineering Contradiction:
Improvetime consumptionVSAvoidsystem stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent applies preliminary action by entering sleep mode before overclocking and using ACPI to pre-configure the memory controller parameters. This allows the system to resume from sleep mode with the overclocking settings already in place, eliminating the need for full reboot and reducing time consumption while maintaining stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using ACPI to monitor and adjust memory controller parameters based on the sleep-resume cycle. This feedback mechanism ensures that the clock rate adjustments are optimized and the system remains stable during dynamic overclocking operations.

Inventive Principle:
Principle #23Feedback

3Productivity

If operating voltage and clock rate are increased to improve system efficiency, then the processing performance is improved, but the power consumption increases

Engineering Contradiction:
Improvesystem efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by enabling the system to dynamically adjust operating voltage and clock rate based on actual workload requirements. Through the sleep-resume cycle with ACPI support, the system can optimize performance parameters when needed while maintaining lower power consumption during idle periods, achieving dynamic balance between productivity and energy usage.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8656150B2Computer system with overclocking function involves setting time parameter of memory controller
Publication Date: 2014.02.18 ASUSTEK COMPUTER INC
  • US8656150B2 patent drawing
  • US8656150B2 patent drawing
  • US8656150B2 patent drawing

AI summary

An overclocking method applied to a computer system includes the following steps: setting a first operating voltage and a first clock rate; generating a first control signal to a power supply and generating a second control signal to a clock generator according to the first operating voltage and the first clock rate, respectively; controlling the computer system into a sleep mode; resuming the computer system from the sleep mode after a predetermined time; restarting the power supply and the clock generator, and generating the first operating voltage by the power supply according to the first control signal and, generating the first clock rate by the clock generator according to the second control signal; and setting a parameter of a memory controller in a north bridge chip of the computer system via the first clock rate and the first operating voltage.