Over-constrained Formal Verification for IC Design
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Solution Overview
Problem
Current formal verification methods for integrated circuit (IC) chip designs are computationally burdensome and time-consuming due to the need to evaluate a vast state space, often missing corner-case bugs and requiring exhaustive mathematical analysis that is impractical for large designs.
Innovation Solution
Implementing an over-constrained formal verification approach that identifies a subset of signals remaining in a constant value over multiple cycles, allowing the application of additional constraints to reduce the state space evaluated during formal verification, thereby decreasing computational burden and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive formal verification is performed on the entire state space, then verification completeness is improved, but computational time and resources increase significantly
Solution Approach 1:
The patent segments the verification process into two phases: first performing a limited formal verification to obtain a counter-example trace, then using that trace to identify and constrain constant signals, thereby segmenting the state space into relevant and irrelevant portions for focused verification
Solution Approach 2:
The patent extracts constant signals from the counter-example trace and uses them to generate over-constraints, effectively taking out and eliminating irrelevant state space portions from the formal verification process
2Productivity
If the state space is reduced by applying over-constraints, then computational burden is decreased, but verification coverage may be limited
Solution Approach 1:
The patent performs preliminary formal verification and counter-example analysis before the main verification, using the obtained trace to identify constant signals and generate over-constraints that guide the subsequent focused verification
Solution Approach 2:
The patent uses feedback from the counter-example trace to iteratively refine the verification process by identifying constant signals and generating over-constraints that improve verification efficiency while maintaining coverage of critical bug scenarios
Data Source
AI summary
In the described examples, an electronic design automation formal verification EDA application is configured to receive an initial evaluation of a circuit design of an integrated circuit (IC) chip. The circuit design of the IC chip includes a list of properties for the IC chip, and the list of properties includes a list of assertions for the IC chip. The formal verification EDA program extracts a counter-example trace from the initial evaluation. The counter-example trace characterizes a set of signals over a plurality of cycles that reach a state in which a given assertion in the list of assertions does not hold true. The formal verification EDA program identifies a subset of signals in the counter-example trace that remain in a specific constant value over the plurality of cycles. The formal verification EDA program executes an over-constrained formal verification for the circuit design.