Automated Overconstrained Input Detection in Formal Verification

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Solution Overview

Problem

Circuit designers face challenges in manually determining whether inputs applied during formal verification are overconstrained, leading to potential undetected errors in circuit design, as the process is prone to human error and lacks certainty.

Innovation Solution

A verification tool is used to establish properties for the environment circuit based on potential constraint sets, applying environmental inputs to determine if the outputs violate these properties, thereby identifying overconstrained inputs automatically.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual constraint verification is performed by circuit designers, then the process is simple and quick, but human error leads to undetected overconstrained inputs and potential design errors

Engineering Contradiction:

Improveformal verification speedVSAvoidconstraint verification accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The verification tool automatically performs constraint verification by itself without requiring manual intervention from circuit designers. The tool establishes properties for the environment circuit, applies environmental inputs, and detects overconstrained inputs through automated property violation detection, making the system self- verifying.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The manual mechanical process of constraint verification by human designers is replaced with an automated computational verification tool that uses formal methods and property-based verification to detect overconstrained inputs, eliminating human error while maintaining verification capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If automated verification tool is used to detect overconstrained inputs, then verification accuracy and certainty are improved, but device complexity and time consumption increase

Engineering Contradiction:

Improveconstraint verification certaintyVSAvoidverification tool complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The verification tool acts as an intermediary between the environment circuit and the CUT, automatically establishing properties and detecting property violations. This intermediary performs the complex verification tasks that would otherwise require manual analysis, managing the complexity while providing certainty.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The verification tool performs preliminary verification of constraints before formal verification of the CUT. By establishing properties for the environment circuit and detecting overconstrained inputs in advance, the tool prevents wasted verification effort and ensures input validity before main verification proceeds.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If comprehensive input constraints are applied to CUT during formal verification, then verification thoroughness is improved, but verification time and computational resources increase

Engineering Contradiction:

Improveverification thoroughnessVSAvoidformal verification time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The verification tool performs preliminary analysis to establish properties for the environment circuit before applying constraints to the CUT. This preliminary action identifies overconstrained inputs in advance, allowing the formal verification to proceed efficiently with only valid, non-overconstrained inputs, thus maintaining thoroughness while reducing time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of applying all possible constraints to the CUT, the verification tool uses partial action by first establishing properties for the environment circuit and only applying constraints that do not violate these properties. This avoids excessive verification time while maintaining sufficient thoroughness for detecting actual design errors.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS7475369B1Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification

Publication Date: 2009.01.06 ORACLE AMERICAN INC

AI summary

Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set. Advantageously, the laborious and error-prone process of manually determining the proper inputs to apply during formal verification is avoided.