Over-current Protection Device Corner Conductive Vias
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Solution Overview
Problem
The manufacturing of small over-current protection devices faces challenges with semi-circular conductive vias, such as misalignment issues during cutting and blockages during inspection and packaging, due to their size and shape, which affects production throughput and yield.
Innovation Solution
The design features four conductive vias placed on the corners of adjacent planar lateral surfaces, allowing for larger cross-sectional areas that provide tolerance in the cutting process and prevent blockages during inspection and packaging, with a ratio of the sum of the cross-sectional areas of the vias to the form factor area ranging from 7%-20%, enabling stable transmission and increased production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semi-circular conductive vias are used in small devices, then manufacturing precision is improved, but device complexity increases and productivity decreases
Solution Approach 1:
The patent divides the single semi-circular via into four separate conductive vias positioned at the corners of the device. This segmentation allows each via to be smaller and positioned away from the cutting path, eliminating the misalignment issue while maintaining adequate conductive area for manufacturing precision without blocking the cutting process.
Solution Approach 2:
The patent transitions from a single via design to a multi-via arrangement in a two-dimensional corner distribution pattern. By placing vias at the four corners rather than using one central semi-circular via, the design achieves better cutting alignment while maintaining electrical conductivity through the combined area of multiple smaller vias.
2Manufacturing precision
If larger semi-circular conductive vias are used, then manufacturing precision is improved, but device complexity increases due to blockages during inspection and packaging
Solution Approach 1:
The patent segments the conductive via function into four separate corner vias instead of one large central via. This segmentation prevents the via from blocking the cutting path and inspection/packaging processes while maintaining adequate total conductive area through the combined cross-section of all four vias.
Solution Approach 2:
The patent uses asymmetric positioning of conductive vias at the four corners of the device rather than a symmetric central semi-circular via. This asymmetric corner placement optimizes the device geometry for cutting and handling processes while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for larger conductive vias that enhance the cutting process tolerance and prevent blockages, thereby increasing production throughput and yield while maintaining device stability during handling and inspection.
Implementation Method 1
The resistive material has positive temperature coefficient (PTC) characteristic that the resistance thereof remains extremely low at room temperature and instantaneously increases to thousand times when the temperature reaches a critical temperature or the circuit has over-current
Data Source
AI summary
An over-current protection device comprises a PTC material layer, first and second conductive layers, first and second electrodes, and four conductive vias. The first and second conductive layers are in physical contact with first and second surfaces of the PTC material layer, respectively. The first electrode contains a pair of first metal foils, and the second electrode contains a pair of second metal foils. The four conductive vias are formed at the corners each defined by two adjacent planar lateral surfaces. Two conductive vias connect the pair of the first metal foils and the first conductive layer, and the other two conductive vias connect the pair of the second metal foils and the second conductive layer. The ratio of the sum of the cross-sectional areas of the conductive vias to a form factor area of the device is in the range of 7% to 20%.