Overdrive Output Buffer Gate Pumping to Reduce MOSFET HCI Stress
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Solution Overview
Problem
Integrated circuits face challenges in interfacing due to different voltage operations, leading to strain on devices and reliability issues, particularly with hot carrier injection (HCI) affecting MOSFETs in overdrive I/O output buffers, which current methods mitigate with costly deep N-well introduction.
Innovation Solution
A novel overdrive output buffer employing gate biasing and pumping techniques reduces peak Vds/Vsb of MOSFETs, eliminating the need for deep N-well and incorporating high-voltage tolerant metal-oxide-metal (MOM) capacitors for improved reliability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep N-well is introduced to mitigate hot carrier injection, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the deep N-well structure from the device architecture, replacing it with an alternative approach that achieves the same reliability goals without the added complexity. The invention removes this specific structural element while maintaining protection against hot carrier injection through different means.
Solution Approach 2:
The patent changes key operating parameters including reducing peak Vds (drain-source voltage) and Vsb (source-bulk voltage) through novel biasing techniques. By modifying these voltage parameters and using gate pumping methods, the device achieves improved reliability without requiring deep N-well structures.
2Reliability
If deep N-well is introduced to mitigate hot carrier injection, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the deep N-well manufacturing step from the fabrication process, thereby reducing manufacturing complexity and cost while maintaining device reliability through alternative biasing and gate pumping techniques.
3Reliability
If gate biasing and pumping techniques are used to reduce peak Vds/Vsb, then reliability is improved and deep N-well is eliminated, but device complexity increases
Solution Approach 1:
The patent employs dynamic gate biasing and pumping techniques that actively adjust voltage levels during operation. This dynamic control reduces peak stress on the device while maintaining simpler structural design, achieving reliability improvement without permanent structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and speed of overdrive circuits, extends device lifetime, and reduces costs by eliminating the need for deep N-well, while maintaining high-voltage tolerance and efficient current supply.
Implementation Method 1
A capacitor has a first electrode electrically connected to a gate electrode of the third transistor, and a second electrode electrically connected to a gate electrode of the first transistor
Data Source
AI summary
An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor.