Overdrive Post Driver Bias Circuit for MOSFET Protection
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Solution Overview
Problem
Conventional overdrive designs for semiconductor chips, particularly those with multiple generations on the same printed circuit board, face reliability issues due to high overdrive voltage damaging transistors and the need for multiplexers, which can further compromise reliability.
Innovation Solution
A post driver with a pull-up and pull-down circuit, along with first and second bias circuits, utilizing PMOS and NMOS transistors in series, and diode strings to provide voltage shifts, replaces conventional multiplexers, ensuring transistors operate within safe voltage regions, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional overdrive voltage (2VDD+VX) is applied to new-generation chips, then compatibility with old-generation chips is achieved, but transistors are damaged due to voltage exceeding safe operating limits
Solution Approach 1:
The patent introduces a post driver circuit as an intermediary component between the power system and the new-generation chip. This post driver includes pull-up and pull-down circuits with PMOS and NMOS transistors that actively regulate the voltage applied to the chip, ensuring the chip receives appropriate voltage (either nominal VDD or overdrive 2VDD+VX) based on operational requirements without direct exposure to potentially damaging voltage levels
Solution Approach 2:
The patent dynamically changes voltage parameters applied to the chip by switching between nominal voltage VDD and overdrive voltage 2VDD+VX based on the operational mode. The post driver controls the gate voltages of transistors to adjust the output voltage level, allowing the same chip to operate safely at different voltage levels without physical modification
2Adaptability or versatility
If multiplexers are used in conventional overdrive design, then voltage switching is achieved, but reliability issues arise due to additional components and potential failure points
Solution Approach 1:
The patent removes the multiplexer component from the overdrive design by implementing voltage switching functionality directly through the post driver circuit. The pull-up and pull-down circuits with controlled PMOS and NMOS transistors perform the voltage switching function that would otherwise require a multiplexer, thereby eliminating the multiplexer and its associated reliability concerns
Solution Approach 2:
The patent merges the voltage switching function with the post driver circuit itself. Instead of having a separate multiplexer component, the post driver integrates the voltage selection and switching logic into its pull-up and pull-down transistor networks, creating a unified circuit that performs both driving and voltage mode switching functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively manages overdrive voltage, protecting transistors from damage and eliminating reliability issues associated with multiplexers, ensuring stable operation across different voltage levels.
Implementation Method 1
The first bias circuit is configured to provide a first voltage shift (VX) between the output terminal of the post driver and the gate terminal of the first PMOS transistor when the pull-down circuit is enabled, to increase the voltage level at the gate terminal of the first PMOS transistor when the pull-down circuit is enabled.
Implementation Method 2
The second bias circuit is configured to provide a second voltage shift (VX) between the output terminal of the post driver and the gate terminal of the first NMOS transistor when the pull-up circuit is enabled, to decrease the voltage level at the gate terminal of the first NMOS transistor when the pull-up circuit is enabled.
Implementation Method 3
The first bias circuit may include a plurality of diodes which are coupled in series to provide the first voltage shift (≈VX) when the pull-down circuit is enabled.
Implementation Method 4
The second bias circuit may include a plurality of diodes which are coupled in series to provide the second voltage shift (≈VX) when the pull-up circuit is enabled.
Data Source
AI summary
A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.