Over-Driving Output Buffer for RC-Delayed Source Driver Signals

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Solution Overview

Problem

As display panel sizes and definitions increase, the resistance-capacitive (RC) delay in source driver circuits becomes larger than the slew rate, preventing unit pixels from reaching the desired target voltage in time, leading to suboptimal image display.

Innovation Solution

An over-driving controller and output buffer unit are introduced to generate buffer output signals with target voltages greater than or less than the predetermined target voltage, using differential amplification and transistor configurations to manage over-driving operations based on enable signals, ensuring timely voltage delivery to display panels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the display panel size and definition are increased, then the image quality and resolution are improved, but the RC delay of the output load becomes larger than the slew rate of the output buffer

Engineering Contradiction:
Improvedisplay definitionVSAvoidsignal rise time
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent applies preliminary action by comparing the current data with previous data before the output buffer generates the output signal. The data comparator determines whether over-driving is needed in advance, and the over-driving controller prepares the appropriate drive strength configuration. This allows the output buffer to immediately apply the correct drive strength when the signal transition is detected, compensating for the increased RC delay caused by larger panel sizes and higher definitions.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If the load resistance and capacitance of the source driver are increased to match larger display panels, then the output voltage target value increases, but the unit pixels cannot reach the desired target voltage within the desired time

Engineering Contradiction:
Improveload capacitanceVSAvoidvoltage reach time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements dynamics by making the drive strength of the output buffer adjustable and variable. The over-driving controller dynamically changes the drive strength based on the comparison between current and previous data, switching between normal drive strength and enhanced over-drive strength. This dynamic adjustment allows the system to adapt to the increased load capacitance and resistance, ensuring that unit pixels reach the desired target voltage within the desired time despite the larger display panel requirements.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively addresses RC delay issues by enabling timely voltage delivery to display panels, ensuring desired images are displayed by adjusting output buffer signals according to current and previous data comparisons, thereby improving display performance.

Implementation Method 1

a first controller configured to: receive the external buffer input signal as a first input signal and the buffer output signal as a second input signal, differentially amplify the first and the second input signals, based on the first and the second over-driver enable signals

Methodology Applied
Scientific EffectDifferential amplification:

Data Source

PatentUS20120026152A1Over-drivable output buffer, source driver circuit having the same, and methods therefor
Publication Date: 2012.02.02 MAGNACHIP SEMICON LTD
  • US20120026152A1 patent drawing
  • US20120026152A1 patent drawing
  • US20120026152A1 patent drawing

AI summary

Provided is an output buffer for a source driver circuit which receives an external buffer input signal and generates a buffer output signal having a predetermined target voltage, the output buffer including: an over-driving controller configured to generate a pair of first internal buffer input signals and a pair of second internal buffer input signals for an over-driving operation, based on a first over-driver enable signal and a second over-driver enable signal, the first and second over-driver signals being provided from an external source, and an output buffer unit configured to: perform the over-driving operation, based on the pair of first internal buffer input signals and the pair of second internal buffer input signals provided from the over-driving controller, and generate: a buffer output signal including a target voltage greater than the predetermined target voltage, or a buffer output signal including a target voltage less than the predetermined target voltage.