Overhang Bridge Interconnect for Semiconductor Packaging
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Solution Overview
Problem
Semiconductor packaging faces challenges with power integrity impairment and signal latency due to undesired loop inductance between the power delivery network and silicon devices in multi-chip or 3-D stacked die assemblies.
Innovation Solution
A semiconductor package architecture that includes an overhang bridge component to couple multiple semiconductor dies while conserving space, with passive components like decoupling capacitors mounted on the bridge component instead of the package or circuit board, reducing loop inductance and improving power integrity and signaling performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive components are mounted on the package or circuit board surface, then the package can accommodate necessary components, but the loop inductance increases and power integrity deteriorates
Solution Approach 1:
The patent moves passive components from the traditional 2D package or circuit board surface to a 3D bridge component structure that spans between semiconductor dies. This dimensional transition allows components to be positioned in the vertical space between dies, reducing the horizontal distance to power delivery networks and minimizing loop inductance while maintaining package functionality.
Solution Approach 2:
The bridge component serves as an intermediary structure between the semiconductor dies and the passive components. Instead of mounting components directly on the package substrate, the bridge component acts as a mediator that positions components closer to the power delivery network, thereby reducing loop inductance and improving power integrity.
2Volume of moving object
If the package size is reduced for miniaturization, then the form factor improves, but the space for mounting passive components becomes limited
Solution Approach 1:
The patent utilizes the vertical dimension between stacked semiconductor dies to mount passive components on the bridge component. This approach transforms the limited 2D surface area into a 3D mounting space, enabling component placement without increasing the package footprint, thus achieving miniaturization while maintaining component mounting capability.
Solution Approach 2:
The bridge component with mounted passive components is nested within the vertical space between semiconductor dies. This nesting approach allows the passive components to occupy the inter-die space rather than requiring additional package volume, enabling package miniaturization while preserving the ability to mount necessary components.
3Reliability
If conventional interconnect structures are used, then the package structure is simple, but signal latency increases and electrical signaling performance deteriorates
Solution Approach 1:
The bridge component creates a vertical interconnect path between semiconductor dies, transitioning from conventional horizontal routing to 3D vertical routing. This dimensional change shortens the signal path length and reduces the number of interconnection layers, thereby decreasing signal latency and improving electrical signaling performance while maintaining structural simplicity.
Data Source
AI summary
An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.