Overhang Semiconductor Chip Stacking via Molded Support
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Solution Overview
Problem
Existing semiconductor packaging techniques face challenges in stacking large-sized chips on small-sized chips without overhangs, ensuring fine pitch electrical connections, and improving heat release characteristics while minimizing electrical shorts.
Innovation Solution
A semiconductor package design that includes a first chip mounted on a package substrate with through-electrodes, a molding layer exposing the second chip's surface, and a non-conductive film between the chips, where the second chip has an overhang supported by the molding layer, and additional features like interconnecting terminals, heat transfer, and radiating layers to enhance electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large-sized semiconductor chip is stacked on a small-sized semiconductor chip, then chip integration density is improved, but overhang occurs causing structural instability
Solution Approach 1:
A support structure extending from the package substrate is introduced as an intermediary element to bear the overhanging portion of the upper chip. This mediator transfers the mechanical load from the unstable overhang to the stable substrate, enabling high-density stacking while maintaining structural integrity.
Solution Approach 2:
The support structure extends in the vertical dimension from the package substrate to reach the overhanging chip region. By utilizing the vertical space and creating a three-dimensional support architecture, the patent resolves the two-dimensional size mismatch between stacked chips.
2Reliability
If through-electrodes are used to connect stacked chips, then electrical connection capability is improved, but manufacturing complexity increases
Solution Approach 1:
Through-electrodes are pre-formed in the package substrate before the stacking process. By preparing the electrical connection pathways in advance, the subsequent chip stacking and bonding processes are simplified, reducing overall manufacturing complexity while ensuring reliable electrical connections.
Data Source
AI summary
A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.