Overhanging Source/Drain Contact Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing source/drain contacts in multi-gate devices, such as FinFETs and MBC transistors, suffer from increased parasitic capacitance due to elongated contacts overlapping adjacent gate structures, leading to performance issues like undesirable ring oscillator performance.
Innovation Solution
A source/drain contact design that spans over multiple active regions, featuring a first portion coupled to a source/drain feature and a second portion that overhangs over an adjacent source/drain feature, separated by a dielectric feature, reducing areal overlap with adjacent gate structures and thus parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If source/drain contacts are elongated to span over multiple active regions, then connectivity is maintained with fewer metal lines, but parasitic capacitance increases due to overlap with adjacent gate structures
Solution Approach 1:
The source/drain contact is designed with an elevated structure that extends vertically above the gate structure level. By utilizing the vertical dimension, the contact can span over multiple active regions and adjacent gate structures without increasing horizontal overlap area, thereby maintaining connectivity while reducing parasitic capacitance.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the source/drain contact and the adjacent gate structures. This mediator allows the contact to extend over the gate structures for connectivity purposes while the insulating material prevents direct electrical interaction, thereby minimizing parasitic capacitance formation.
2Device complexity
If source/drain contacts overlap adjacent gate structures to maintain connectivity, then fewer metal lines are needed, but ring oscillator performance deteriorates due to increased parasitic capacitance
Solution Approach 1:
The contact structure is elevated to extend above the gate structure level, utilizing vertical space to reduce horizontal overlap. This dimensional change allows the contact to maintain connectivity across multiple regions while minimizing the overlapping area with gate structures, thereby reducing parasitic capacitance and improving ring oscillator performance.
Solution Approach 2:
An insulating layer is positioned between the source/drain contact and adjacent gate structures to act as a mediator. This intermediary prevents direct capacitive coupling while allowing the contact to extend over the gate structures for connectivity, thus maintaining device simplicity while improving oscillator performance.
Data Source
AI summary
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.