Overlaid Erase Block Mapping for Flash Memory Wear-Leveling
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Solution Overview
Problem
Flash memory endurance is limited by the degradation of programming and erasing characteristics due to wear-leveling inefficiencies, leading to uneven program/erase cycles across physical erase blocks, which affects both data storage and system management information allocation, resulting in reduced memory lifespan and increased boot times.
Innovation Solution
The implementation of an overlaid erase block mapping scheme that includes a super system erase block with pointers, allowing for efficient wear-leveling and reduced mount latency by mapping system and data erase blocks independently and using reserved blocks for garbage collection, while ensuring even erase counts across all physical erase blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional EB mapping schemes are used, then wear-leveling is performed, but P/E cycles are not distributed evenly across physical EBs, reducing flash memory lifespan
Solution Approach 1:
The flash memory is divided into multiple groups, with each group containing multiple physical erase blocks. The mapping scheme operates at the group level rather than individual block level, segmenting the wear-leveling process to achieve more uniform P/E cycle distribution across all physical EBs.
Solution Approach 2:
The patent implements a hierarchical mapping structure where logical erase blocks are mapped to physical erase blocks within groups, and groups are organized within the flash memory. This nested structure allows multi-level wear-leveling optimization, improving overall P/E cycle distribution uniformness.
2Loss of time
If system EBs and data EBs are mapped together, then storage space is optimized, but mount latency increases during boot operation
Solution Approach 1:
The patent separates system EBs and data EBs into different groups within the flash memory. During mount operation, only the group containing system EBs needs to be accessed, reducing mount latency. This segmentation allows independent management of system and data blocks.
Solution Approach 2:
The super system EB is pre-mapped to a specific physical EB in a dedicated group during initialization. This preliminary mapping ensures that during boot operation, the system can directly access the known physical location of system EBs without scanning the entire flash memory, significantly reducing mount latency.
3Reliability
If reserved EBs are not allocated, then storage capacity is maximized, but garbage collection cannot reclaim failed EBs
Solution Approach 1:
The patent allocates reserved EBs in each group that are not used for storing user data or system information. These reserved EBs are specifically designated for garbage collection operations, allowing the system to reclaim failed or worn-out EBs by migrating their data to reserved EBs and then erasing the old blocks. This ensures continuous operation capability.
Data Source
AI summary
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.