Overlap FDE Digital Filter Clocking for Lower Circuit Scale
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Solution Overview
Problem
The overlap FDE method requires higher processing throughput due to increased operations in the overlapped part, leading to increased circuit scale and power consumption, especially when parallelizing the FDE processing circuit.
Innovation Solution
A digital filter circuit and method that includes an overlap addition mechanism, FFT processing, filter computation, IFFT processing, and overlap removal, with a clock generation mechanism setting the filter processing clock frequency based on the number of overlaps, optimizing the throughput and reducing circuit scale and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallelizing the FDE processing circuit is used to improve processing throughput, then the processing throughput of FDE is improved, but the circuit scale and electric power consumption increase
Solution Approach 1:
The patent applies dynamics by making the circuit configuration adaptable through dynamic selection between single-processing-mode and parallel-processing-mode based on real-time throughput requirements. The system transitions between operational states rather than being statically configured, allowing optimal balance between throughput and circuit scale.
Solution Approach 2:
The FDE processing circuit is segmented into multiple processing units that can be independently activated. Instead of always operating in full parallel mode, the system divides the processing into selectable segments (single mode or parallel mode), enabling flexible resource utilization and reducing circuit scale when full parallel processing is not required.
2Productivity
If parallelizing the FDE processing circuit is used to improve processing throughput, then the processing throughput of FDE is improved, but the electric power consumption increases
Solution Approach 1:
The system dynamically adjusts its operational mode based on throughput requirements, switching between single-processing-mode (lower power) and parallel-processing-mode (higher power). This dynamic adaptation ensures that power consumption is optimized for each operational context rather than operating at maximum power continuously.
Solution Approach 2:
Different processing units within the circuit have different activation states based on local requirements. The system activates only the necessary processing units (either one or multiple) based on the current throughput demand, ensuring that power is consumed only where and when needed rather than uniformly across the entire circuit.
3Productivity
If increasing the processing throughput for overlapped part is implemented, then the FDE processing capability is improved, but the circuit configuration becomes complex requiring flow control
Solution Approach 1:
The circuit configuration is made dynamic by allowing selection between single-processing-mode and parallel-processing-mode. This dynamic configurability simplifies the overall design by providing a unified circuit structure that can adapt its complexity level based on operational needs, rather than requiring separate complex flow control mechanisms for different throughput levels.
Solution Approach 2:
The same FDE processing circuit is designed to perform multiple functions through mode selection - it can operate in both single-processing-mode and parallel-processing-mode using the same hardware resources. This multi-functionality eliminates the need for separate dedicated circuits for different throughput requirements, simplifying the overall circuit configuration.
Data Source
AI summary
A digital filter circuit and a digital filter control method are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method. The digital filter circuit according to the present invention includes: an overlap addition unit for giving an overlap of M data (M is a positive integer) between the block and the previous block; an FFT processing unit for transforming the generated block by FFT processing; a filter computation unit for performing filter processing to the transformed block; an IFFT unit for transforming the block, which the filter processing was performed to, by IFFT processing; an overlap removal unit for removing M units of data from both ends of the transformed block; and a clock generation unit for setting the frequency of a filter processing clock signal based on a value of M, wherein the filter processing clock signal drives the data output unit of the overlap addition unit, the FFT unit, the filter computation unit, the IFFT unit, and the input unit of the overlap removal unit.