Overlap FFT Digital Filter Clocking for Lower Power FDE
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Solution Overview
Problem
The overlap FDE method requires higher processing throughput due to increased operations in the overlapped part, leading to increased circuit scale and power consumption, which is inefficient.
Innovation Solution
A digital filter circuit with an overlap addition, FFT processing, filter computation, IFFT processing, and overlap removal, where the filter processing clock signal is set based on the number of overlaps to minimize power consumption and circuit scale, with the frequency determined as N/(N-M) times the input-output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallelizing the FDE processing circuit is used to improve processing throughput, then the processing throughput is improved, but the circuit scale and power consumption increase
Solution Approach 1:
The patent applies dynamics by making the circuit configuration reconfigurable based on the overlap parameter M. The FFT block size is dynamically adjusted according to the overlap amount, allowing the system to adapt its processing capacity to match the actual computational requirements. This prevents the circuit from being oversized for all operating conditions, thereby reducing circuit scale and power consumption while maintaining adequate processing throughput.
Solution Approach 2:
The patent changes the parameter of FFT block size based on the overlap parameter M. By adjusting the FFT block size parameter according to the actual overlap amount required, the system optimizes the balance between processing throughput and circuit complexity. This parameter adaptation allows the circuit to operate efficiently without requiring maximum parallelization in all cases.
2Productivity
If parallelizing the FDE processing circuit is used to improve processing throughput, then the processing throughput is improved, but the power consumption increases
Solution Approach 1:
The patent makes the circuit operation dynamic by configuring the FFT block size according to the overlap parameter M. This dynamic configuration ensures that the power consumption is proportional to the actual processing requirements rather than being fixed at a high level for all cases, thereby reducing overall power consumption while maintaining necessary processing throughput.
Solution Approach 2:
The patent changes the operational parameters (FFT block size) based on the overlap amount M, which directly affects power consumption. By adjusting these parameters to match the actual processing load, the system avoids unnecessary power consumption associated with over-provisioned parallel processing circuits.
3Productivity
If the FFT block size is increased to handle overlap processing, then the processing capability is improved, but the circuit scale increases
Solution Approach 1:
The patent changes the FFT block size parameter based on the overlap parameter M. By adjusting the block size to match the actual overlap requirements rather than using a fixed large block size, the system achieves necessary processing capability with a smaller, more compact circuit implementation.
Solution Approach 2:
The patent implements dynamic configuration where the FFT block size is determined by the overlap parameter M. This allows the circuit scale to be optimized for each specific operating condition, preventing the need for a consistently large circuit design and thereby reducing overall device complexity.
Data Source
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AI summary
[Objective] To provide a digital filter circuit and a digital filter control method which are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method. [Solution] A digital filter circuit according to the present invention includes: an overlap addition means for giving an overlap of M data (M is a positive integer) between the block and the previous block; an FFT processing means for transforming the generated block by FFT processing; a filter computation means for performing filter processing to the transformed block; an IFFT means for transforming the block, which the filter processing was performed to, by IFFT processing; an overlap removal means for removing M units of data from both ends of the transformed block; and a clock generation means for setting the frequency of a filter processing clock signal based on a value of M, wherein the filter processing clock signal drives the data output unit of the overlap addition means, the FFT means, the filter computation means, the IFFT means, and the input unit of the overlap removal means.