3D Memory Via Structure Using Overlapped Staircase and Coupling Parts
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Solution Overview
Problem
The challenge in three-dimensional memory devices is to increase the degree of integration while managing the increased number of word lines, which leads to a higher number of wiring lines, resulting in a decrease in integration due to the need for more coupling wiring lines.
Innovation Solution
The solution involves a three-dimensional memory device structure with stacked word lines and interlayer dielectric layers, where the upper and lower stacks have overlapping staircase and coupling parts, allowing for efficient vertical via placement without separate openings, and wider pad areas to prevent alignment failures during via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to increase the degree of integration, then the memory capacity is improved, but the number of wiring lines needed to couple the word lines and row decoder increases, resulting in decreased degree of integration
Solution Approach 1:
The patent transitions from a planar wiring layout to a three-dimensional stacked architecture. Multiple word line stacks are arranged vertically, with coupling parts extending in the vertical direction to connect word lines across different stacks. This dimensional transition allows numerous word lines to be integrated without proportionally increasing the horizontal wiring area, thereby maintaining high degree of integration despite the increased number of word lines.
Solution Approach 2:
The coupling part is designed to extend parallel to the vertical direction and nest within the spatial envelope of the word line stacks. The coupling part accommodates multiple wiring lines that are bundled together, effectively nesting the wiring infrastructure within the existing three-dimensional structure rather than requiring separate planar wiring layers for each connection.
2Reliability
If separate openings are formed for vertical vias to pass through staircase and coupling parts, then via connectivity is achieved, but the number of openings increases process complexity and reduces manufacturing precision
Solution Approach 1:
The patent merges the openings for vertical vias that pass through the staircase part with the openings for vertical vias that pass through the coupling part. A single opening simultaneously accommodates multiple vertical vias, including those connecting to the staircase part and those connecting to the coupling part. This consolidation reduces the total number of openings required, simplifies the photolithography and etching processes, and improves alignment accuracy by reducing the cumulative alignment errors that would arise from multiple separate opening formation steps.
Data Source
AI summary
A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.