Overlapping Active Clamps for Multi-Domain ESD Protection
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Solution Overview
Problem
Integrated circuits with multiple power domains face challenges in electrostatic discharge (ESD) protection due to the complexity of discharge paths and the need for substantial layout area, especially when I/O buffers from different power domains are interspersed, which can lead to inadequate protection against ESD events.
Innovation Solution
The implementation of a multiple power domain integrated circuit design that includes overlapping active clamps and trigger circuitry across I/O cells, with separate power and ESD rails for each domain, allowing for parallel operation of shunting devices and distributed trigger circuits to effectively dissipate ESD events and minimize IR drops along power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate ESD protection circuits are implemented for each power domain, then ESD protection reliability is improved, but layout area increases substantially
Solution Approach 1:
The patent merges ESD protection circuits from different power domains into shared layout regions. Multiple active clamps from different power domains are allowed to overlap in the same physical space, reducing the total layout area while maintaining protection for each domain. The trigger circuits are also shared across domains, further reducing area requirements.
Solution Approach 2:
The patent implements universal trigger circuits that can detect ESD events across multiple power domains simultaneously. A single trigger circuit can activate multiple active clamps belonging to different power domains, making the protection system multi-functional and reducing the need for separate dedicated circuits for each domain.
2Adaptability or versatility
If I/O buffers for different power domains are interspersed, then power domain integration is improved, but ESD protection complexity increases
Solution Approach 1:
The patent segments the ESD protection system into independent active clamp units, each associated with a specific power domain, while allowing these segments to be distributed and interspersed throughout the layout. Each I/O buffer region has its own active clamp for its power domain, but the overall system manages multiple domains through shared trigger circuits and overlapping protection regions.
Solution Approach 2:
The patent introduces trigger circuits as intermediary components that mediate between multiple power domains and their respective active clamps. The trigger circuits detect ESD events and coordinate the activation of appropriate clamps across different domains, simplifying the overall control logic while maintaining the ability to handle interspersed I/O buffers from multiple domains.
3Speed
If active clamps are placed closer to I/O pads, then ESD response time is improved, but power rail resistance impact increases
Solution Approach 1:
The patent addresses the power rail resistance issue by allowing active clamps from different power domains to overlap in the same physical region. This dimensional arrangement creates multiple parallel discharge paths through different power domains, effectively reducing the impact of resistance in any single power rail while maintaining close proximity to I/O pads for fast response.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances ESD protection by ensuring that ESD events are detected and addressed closer to the affected I/O pads, reducing the impact of power rail resistance and allowing for more compact and modular layouts, thereby improving the overall performance and reliability of ESD protection circuits.
Implementation Method 1
An ESD event may occur, for example, when a user who has accumulated electrostatic charge picks up a CMOS IC. The accumulated charge may cause an instantaneous voltage of a few thousand volts to appear across terminals of the IC.
Implementation Method 2
These circuits typically include diodes to discharge a large voltage appearing on a signal terminal into a power supply terminal. Designers also typically include active power supply voltage rail clamps that become active to quickly dissipate a voltage between the power and ground power supply voltage terminals built up during an ESD event.
Data Source
AI summary
An integrated circuit (300/400) includes first and second power domains and a bank of input/output (I/O) cells (305/405) coupled to the first and second power domains. The bank of I/O cells (305/405) includes a first plurality of active clamps (374/445) for the first power domain and a second plurality of active clamps (384/425) for the second power domain wherein the first (374/445) and second (384/425) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element (425, 445) for a respective second power domain. According to another aspect, each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.